adc12l066civyx National Semiconductor Corporation, adc12l066civyx Datasheet - Page 21

• Manufacturer Part Number: adc12l066civyx
• Description: 12-bit, 66 Msps, 450 Mhz Bandwidth A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Applications Information
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase with each other, the full scale
error in LSB can be described as approximately
Where dev is the angular difference between the two signals
having a 180˚ relative phase relationship to each other (see
Figure 3). Drive the analog inputs with a source impedance
less than 100Ω.
For differential operation, each analog input pin of the differ-
ential pair should have a peak-to-peak voltage equal to the
input reference voltage, V
1.3.1 SINGLE-ENDED INPUT OPERATION
Single-ended performance is inferior to that with differential
input signals, so single-ended operation is not recom-
mended, However, if single-ended operation is required and
the resulting performance degradation is acceptable, one of
the analog inputs should be connected to the d.c. mid point
voltage of the driven input. The peak-to-peak differential
input signal should be twice the reference voltage to maxi-
mize SNR and SINAD performance (Figure 2b).
For example, set V
V
Because very large input signal swings can degrade distor-
tion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
while maintaining a full-range output. Table 1 and Table 2
indicate the input to output relationship of the ADC12L066.
IN
+ with a signal range of 0.5V to 1.5V.
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
FIGURE 2. Expected Input Signal Range
REF
E
to 0.5V, bias V
FS
Distortion
REF
= dev
, and be centered around V
1.79
20032812
IN
− to 1.0V and drive
20032811
(Continued)
CM
.
21
1.3.2 DRIVING THE ANALOG INPUTS
The V
an analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
spikes at the signal input pins. As a driving amplifier attempts
to counteract these voltage spikes, a damped oscillation
may appear at the ADC analog input. The best amplifiers for
driving the ADC12L066 input pins must be able to react to
these spikes and settle before the switch opens and another
sample is taken. The LMH6702 LMH6628, LMH6622 and the
LMH6655 are good amplifiers for driving the ADC12L066.
To help isolate the pulses at the ADC input from the amplifier
output, use RCs at the inputs, as can be seen in Figure 5
and Figure 6. These components should be placed close to
the ADC inputs because the input pins of the ADC is the
most sensitive part of the system and this is the last oppor-
tunity to filter that input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered with setting the RC pole. Setting the
pole in this manner will provide best SINAD performance.
To obtain best SNR performance, leave the RC values as
calculated. To obtain best SINAD and ENOB performance,
reduce the RC time constant until SNR and THD are numeri-
cally equal to each other. To obtain best distortion and SFDR
performance, eliminate the RC altogether.
For undersampling applications, the RC pole should be set
at about 1.5 to 2 times the maximum input frequency for
narrow band applications. For wide band applications, the
RC pole should be set at about 1.5 times the maximum input
frequency to maintain a linear delay response.
A single-ended to differential conversion circuit is shown in
Figure 5 and Table 3 gives resistor values for that circuit to
provide input signals in a range of 1.0V
differential input pins of the ADC12L066.
1.3.3 INPUT COMMON MODE VOLTAGE
The input common mode voltage, V
range of 0.5V to 1.5V and be of a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than 0.8 Volts below the V
supply voltage. The nominal V
1.0V, but V
as no d.c. current is drawn from either of these pins.
2.0 DIGITAL INPUTS
Digital inputs are TTL/CMOS compatible and consist of CLK,
OE and PD.
0 - 0.25V
SIGNAL
RANGE
0 - 0.5V
±
TABLE 3. Resistor values for Circuit of Figure 5
0.25V
IN
+ and the V
RM
or V
100Ω
open
0Ω
R1
RN
IN
− inputs of the ADC12L066 consist of
can be used as a V
openΩ
698Ω
0Ω
R2
CM
should generally be about
124Ω
499Ω
100Ω
R3
CM
±
, should be in the
0.5V at each of the
CM
1500Ω 1000Ω
1500Ω
698Ω
R4
source as long
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R5, R6
499Ω
499Ω
A