adc12l066civyx National Semiconductor Corporation, adc12l066civyx Datasheet - Page 22

• Manufacturer Part Number: adc12l066civyx
• Description: 12-bit, 66 Msps, 450 Mhz Bandwidth A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Applications Information
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 1 MHz to 80 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency is too low, the charge on
internal capacitors can dissipate to the point where the ac-
curacy of the output data will degrade. This is what limits the
lowest sample rate to 1 MSPS.
The duty cycle of the clock signal can affect the performance
of any A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12L066 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 40% to 60%.
The clock line should be series terminated at the clock
source in the characteristic impedance of that line if the clock
line is longer than
where t
of the signal along the trace. For a typical board of FR-4
material, t
pin may need to be a.c. terminated with a series RC such
that the resistor value is equal to the characteristic imped-
ance of the clock line and the capacitor value is
where "I" is the line length in inches and Z
istic impedance of the clock line. This termination should be
located as close as possible to, but within one centimeter of,
the ADC12L066 clock pin as shown in Figure 6. It should
also be located beyond the ADC clock pin as seen from the
clock source.
Take care to maintain a constant clock line impedance
throughout the length of the line and to properly terminate
the source end of the line with its characteristic impedance.
Refer to Application Note AN-905 for information on setting
characteristic impedance.
2.2 OE
The OE pin, when high, puts the output pins into a high
impedance state. When this pin is low the outputs are in the
active state. The ADC12L066 will continue to convert
whether this pin is high or low, but the output can not be read
while the OE pin is high.
Since ADC noise increases with increased output capaci-
tance at the digital output pins, do use the TRI-STATE out-
r
is the clock rise time and t
PROP
is about 150 ps/in, or 60 ps/cm. The CLOCK
prop
is the propagation rate
o
is the character-
(Continued)
22
puts of the ADC12L066 to drive a bus. Rather, each output
pin should be located close to and drive a single digital input
pin. To further reduce ADC noise, a 100 Ω resistor in series
with each ADC digital output pin, located close to their re-
spective pins, should be added to the circuit. See Section
3.0.
2.3 PD
The PD pin, when high, holds the ADC12L066 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 50 mW
with a 66 MHz clock and 30 mW if the clock is stopped. The
output data pins are undefined in this mode. The data in the
pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the capacitors on pins 30, 31 and 32 and is about
300 ns with the recommended 0.1 µF on these pins. These
capacitors loose their charge in the Power Down mode and
must be recharged by on-chip circuitry before conversions
can be accurate. Smaller capacitor values allow faster re-
covery from the power down mode, but can result in a
reduction in SNR, SINAD and ENOB performance.
3.0 OUTPUTS
The ADC12L066 has 12 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the OE and PD pins are low. While the t
information about output timing, a simple way to capture a
valid output is to latch the data on the rising edge of the
conversion clock (pin 10). However, which edge to use might
depend upon the clock frequency and duty cycle. If the rising
edge is used, the t
mine required setup and hold times of the data inputs of the
driven device. If the falling edge of the clock is used, care
must be taken to be sure that adequate setup and hold times
are allowed for capturing the ADC output data.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally,
bus capacitance beyond the specified 15 pF/pin will cause
t
output data. The result could be an apparent reduction in
dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connect-
ing buffers between the ADC outputs and any other circuitry
(74ACQ541, for example). Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of 100Ω at the digital outputs, close to the ADC
pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could oth-
erwise result in performance degradation. See Figure 4.
While the ADC12L066 will operate with V
to 1.8V, t
external timing when using reduced V
OD
to increase, making it difficult to properly latch the ADC
OD
DR
and DR GND. These large charging current
increases with reduced V
OD
and t
OH
times can be used to deter-
DR
.
DR
DR
OD
. Be careful of
voltages down
time provides