adc12dl066civs National Semiconductor Corporation, adc12dl066civs Datasheet - Page 8

• Manufacturer Part Number: adc12dl066civs
• Description: Dual 12-bit, 66 Msps, 450 Mhz Input Bandwidth A/d Converter W/internal Reference
• Manufacturer: National Semiconductor Corporation

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Symbol
t
t
t
t
t
AJ
HOLD
DIS
EN
PD
AC Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (-
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 3). However, errors in the A/D conversion can occur if the input goes above V
input voltage must be ≤+3.4V to ensure accurate conversions.
Note 8: To guarantee accuracy, it is required that |V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for external reference applications.
Note 14: I
V
voltage, C
Note 15: Excludes I
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for T
DR
, and the rate at which the outputs are switching (which is signal dependent). I
n
DR
is total capacitance on the output pin, and f
Aperture Jitter
Clock Edge to Data Transition
Data outputs into Hi-Z Mode
Data Outputs Active after Hi-Z
Mode
Power Down Mode Exit Cycle
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
DR
. See note 14.
Parameter
J
= T
J
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
MIN
REF
JA
= +1.0V (2V
to T
), and the ambient temperature, (T
MAX
: all other limits T
A
P-P
–V
n
D
differential input), the 12-bit LSB is 488 µV.
is the average frequency at which that pin is toggling.
J
| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
REF
0.1 µF on pins 4, 14; series 1.5 Ω & 1
µF between pins 5, 6 and between
pins 12, 13
IL
(Continued)
= +1.0V, f
= 0.4V for a falling edge and V
J
= 25˚C (Notes 7, 8, 9, 12)
A
CLK
), and can be calculated using the formula P
Conditions
8
DR
IN
A
= 66 MHz, f
or below GND by more than 100 mV. As an example, if V
=V
<
DR
AGND, or V
A
or below GND will not damage this device, provided current is limited per
(C
0
x f
20055207
0
+ C
IH
IN
IN
1
= 2.4V for a rising edge.
>
= 10 MHz, t
x f
V
1
A
+....C
), the current at that pin should be limited to 25 mA. The
11
x f
(Note 10)
11
r
Typical
) where V
= t
500
1.2
10
10
8
f
D
= 2 ns, C
MAX = (T
DR
A
is the output driver power supply
(Note 10)
= V
Limits
J
max - T
L
D
= 15 pF/pin. Bold-
A
= +3.3V, V
is +3.3V, the full-scale
A
)/θ
JA
. The values
(Limits)
ps rms
Units
J
DR
max, the
ns
ns
ns
µs
=