adc12dl066civs National Semiconductor Corporation, adc12dl066civs Datasheet - Page 19

• Manufacturer Part Number: adc12dl066civs
• Description: Dual 12-bit, 66 Msps, 450 Mhz Input Bandwidth A/d Converter W/internal Reference
• Manufacturer: National Semiconductor Corporation

Applications Information
erally be about V
a V
of these pins.
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, OEA,
OEB, OF, INT/EXT REF and PD.
2.1 The CLK Pin
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 15 MHz to 75 MHz with rise and fall times of 2
ns or less. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
If the CLK is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample.
The ADC clock line should be considered to be a transmis-
sion line and be series terminated at the source end to match
the source impedance with the characteristic impedance of
the clock line. It generally is not necessary to terminate the
far (ADC) end of the clock line, but if a single clock source is
driving more than one device (a condition that is generally
not recommended), far end termination may be needed. The
far end termination should be near but beyond the ADC clock
pin as seen from the clock source.
It is highly desirable that the the source driving the ADC CLK
pin only drive that pin. However, if that source is used to
drive other things, each driven pin should be a.c. terminated
with a series RC to ground, as shown in Figure 4, such that
the resistor value is equal to the characteristic impedance of
the clock line and the capacitor value is
where t
is the line length and Z
the clock line. This termination should be as close as pos-
sible to the ADC clock pin but beyond it as seen from the
clock source. Typical t
FR-4 board material. The units of "L" and t
same (inches or centimeters).
The duty cycle of the clock signal can affect the performance
of any A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12DL066 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 43% to 57% at 66 Msps.
Take care to maintain a constant clock line impedance
throughout the length of the line. Refer to Application Note
AN-905 for information on setting characteristic impedance.
2.2 The OEA, OEB Pins
The OEA and OEB pins, when high, put the output pins of
their respective converters into a high impedance state.
When either of these pins is low, the corresponding outputs
are in the active state. The ADC12DL066 will continue to
convert whether these pins are high or low, but the output
can not be read while the pin is high.
CM
source as long as no d.c. current is drawn from either
PD
is the signal propagation tine in ns/unit length, "L"
REF
/2, but V
PD
O
is about 150 ps/inch (60 ps/cm) on
is the characteristic impedance of
RB
A and V
RB
B can be used as
PD
(Continued)
should be the
19
Since ADC noise increases with increased output capaci-
tance at the digital output pins, do not use the TRI-STATE
outputs of the ADC12DL066 to drive a bus. Rather, each
output pin should be located close to and drive a single
digital input pin. To further reduce ADC noise, a 100 Ω
resistor in series with each ADC digital output pin, located
close to their respective pins, should be added to the circuit.
2.3 The PD Pin
The PD pin, when high, holds the ADC12DL066 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 75 mW
with a 66 MHz clock and 40mW if the clock is stopped when
PD is high. The output data pins are undefined in the power
down mode and the data in the pipeline is corrupted while in
the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on pins 4, 5, 6, 12, 13 and 14 and
is about 500 µs with the recommended components on the
V
loose their charge in the Power Down mode and must be
recharged by on-chip circuitry before conversions can be
accurate. Smaller capacitor values allow slightly faster re-
covery from the power down mode, but can result in a
reduction in SNR, SINAD and ENOB performance.
2.4 The OF Pin
The output data format is offset binary when the OF pin is at
a logic low or 2’s complement when the OF pin is at a logic
high. While the sense of this pin may be changed "on the fly,"
doing this is not recommended as the output data could be
erroneous for a few clock cycles after this change is made.
2.5 The INT/EXT REF Pin
The INT/EXT REF pin determines whether the internal ref-
erence or an external reference voltage is used. With this pin
at a logic low, the internal 1.0V reference is in use. With this
pin at a logic high an external reference must be applied to
the V
There is no need to bypass the V
reference is used. There is no access to the internal refer-
ence voltage, but its value is approximately equal to V
V
3.0 DATA OUTPUT PINS
The ADC12DL066 has 24 TTL/CMOS compatible Data Out-
put pins. Valid data is present at these outputs while the OE
and PD pins are low. While the t
about output timing, t
frequency. At the rated 66 MHz clock rate, the data transition
can be coincident with the rise of the clock and about 7 ns
before the fall of the clock (depending upon V
falling edge of the clock should be used to capture the output
data. At lower clock frequencies the data transition occurs a
little after the rising edge of the clock, but the fall of the clock
still appears to be the best edge for data capture. However,
circuit board layout will affect relative delays of the clock and
data, so it is important to consider these relative delays when
designing the digital interface.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
RP
RN
, V
. See Section 1.2
REF
RM
and V
pin, which should then be bypassed to ground.
DR
and DR GND. These large charging current
RN
reference bypass pins. These capacitors
OD
will change with a change of clock
OD
REF
time provides information
pin when the internal
DR
www.national.com
), so the
RP
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