m48t86 STMicroelectronics, m48t86 Datasheet - Page 22

• Manufacturer Part Number: m48t86
• Description: 5v Pc Real Time Clock
• Manufacturer: STMicroelectronics

PF: periodic interrupt flag
AF: alarm flag
UF: update ended interrupt flag
BIT 0 through 3: unused bits
Register D
VRT: valid RAM and time
BIT 0 through 6: unused bits
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The Periodic Interrupt Flag (PF) is a “Read only” bit which is set to a '1' when an edge is
detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic
rate. PF is set to a '1' independent of the state of the PIE Bit. The IRQ signal is active and
will set the IRQF Bit. The PF Bit is cleared by a RST or a software READ of Register C.
A '1' in the AF (Alarm Interrupt Flag) Bit indicates that the current time has matched the
alarm time. If the AIE Bit is also a '1,' the IRQ pin will go low and a '1' will appear in the IRQF
Bit. A RST or a READ of Register C will clear AF.
The Update Ended Interrupt Flag (UF) Bit is set after each update cycle. When the UIE Bit is
set to a '1,' the '1' in the UF Bit causes the IRQF Bit to be a '1.' This will assert the IRQ pin.
UF is cleared by reading Register C or a RST.
Bit 3 through Bit 0 are unused. These bits always read '0' and cannot be written.
The Valid RAM and Time (VRT) Bit is set to the '1' state by STMicroelectronics prior to
shipment. This bit is not writable and should always be a '1' when read. If a '0' is ever
present, an exhausted internal lithium cell is indicated and both the contents of the RTC
data and RAM data are questionable. This bit is unaffected by RST.
The remaining bits of Register D are not usable. They cannot be written and when read,
they will always read '0.'
Table 7.
Table 8.
IRQF
BIT7
BIT7
VRT
Register C MSB
Register D MSB
BIT6
BIT6
PF
0
BIT5
BIT5
AF
0
BIT4
BIT4
UF
0
BIT3
BIT3
0
0
BIT2
BIT2
0
0
BIT1
BIT1
0
0
BIT0
BIT0
0
0