m48t86 STMicroelectronics, m48t86 Datasheet

Page 1

... Pin and function compatible with bq3285/7A and DS12887 ■ RoHS compliant – Lead-free second level interconnect July 2007 5 real-time clock 24 1 PCDIP24 (PC) Battery/Crystal CAPHAT SNAPHAT (SH) Battery/Crystal 28 1 SOH28 (MH) Rev 6 M48T86 1/36 www.st.com 1 ...

Page 2

Contents Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

PIE: periodic interrupt enable ...

Page 4

List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

... Summary description The M48T86 is an industry standard Real Time Clock (RTC). The M48T86 is composed of a lithium energy source, quartz crystal, write protection circuitry, and a 128-byte RAM array. This provides the user with a complete subsystem packaged in either a 24-pin DIP CAPHAT™ or 28-pin SNAPHAT volatile time-of-day clock, alarm interrupts, a one-hundred-year clock with programmable interrupts, square wave output, and 128 bytes of non-volatile static RAM ...

Page 7

... CC V Ground SS NC Not connected internally Figure 2. 24-pin DIP connections MOT SQW AD0 4 21 RCL AD1 AD2 6 19 IRQ M48T86 AD3 7 18 RST AD4 AD5 AD6 10 15 R/W AD7 AI01641 7/36 ...

Page 8

... Figure 3. 28-pin SOIC connections Figure 4. Block diagram BAT DS R/W AS AD0-AD7 8/ MOT AD0 5 AD1 6 AD2 7 M48T86 AD3 8 AD4 9 AD5 10 AD6 11 AD7 AI01642 OSCILLATOR / 8 PERIODIC INTERRUPT/SQUARE WAVE SELECTOR POWER V CC SWITCH POK AND WRITE PROTECT ...

Page 9

... M48T86 latches the address present on AD0-AD7. Valid WRITE data must be present and held stable during the latter portion of the R/W pulse (see In a READ cycle, the M48T86 outputs 8 bits of data during the latter portion of the DS pulse. The READ cycle is terminated and the bus returns to a high impedance state upon a high transition on R/W ...

Page 10

... READ cycle. This is very similar to an Output Enable (G) signal on other memory devices. E (chip enable input) The Chip Enable pin must be asserted low for a bus cycle in the M48T86 to be accessed. Bus cycles which take place without asserting E will latch the addresses present, but no data access will occur. ...

Page 11

... R/W (read/write input) The R/W pin is used to latch data into the M48T86 and provides functionality similar other memory systems. Non-volatile RAM The 114 general-purpose non-volatile RAM bytes are not dedicated to any special function within the M48T86. They can be used by the processor program as non-volatile memory and are fully accessible during the update cycle ...

Page 12

Figure 7. Motorola bus read/write mode AC waveforms AS tDAS DS R/W E AD0-AD7 (Write) AD0-AD7 (Read) 12/36 tASW tASD tCYC tDSL tDSH tRWS tCS tAH tAS tAS tOD tAH tRWH tCH tDW tDHW tDHR AI01649 ...

Page 13

... WRITE setup time DW t Delay time before update cycle BUC (2) t Periodic interrupt time interval PI t Time of update cycle UC 1. Valid for ambient operating temperature See Table 4 on page 18. M48T86 (1) Min Typ 160 ...

Page 14

... Clock operations Address map The address map of the M48T86 is shown in 10 bytes of RAM that contain the RTC time, calendar and alarm data, and 4 bytes which are used for control and status. All bytes can be read or written to except for the following: 1. Registers C & D are “Read only.” ...

Page 15

Figure 8. Address map 0 14 CLOCK AND CONTROL BYTES STATUS REGISTERS 13 14 114 STORAGE REGISTERS BYTES 127 Table 3. Time, calendar, and alarm formats Address RTC Bytes 0 Seconds 1 Seconds alarm 2 Minutes 3 Minutes alarm Hours, ...

Page 16

... Determination that the RTC initiated an interrupt is accomplished by reading Register C. A logic '1' in the IRQF Bit indicates that one or more interrupts have been initiated by the M48T86. The act of reading Register C clears all active flag bits and the IRQF Bit. Periodic interrupt The periodic interrupt will cause the IRQ pin active state from once every 500ms to once every 122µ ...

Page 17

... All other combinations of Bits 4-6 keep the oscillator off. Update cycle The M48T86 executes an update cycle once per second regardless of the SET Bit (Register B; Bit 7). When the SET Bit is asserted, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments ...

Page 18

The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP Bit is set ...

Page 19

Register A UIP update in progress The Update in Progress (UIP) Bit is a status flag that can be monitored. When the UIP Bit is '1,' the update transfer will soon occur (see will not occur for at least 244µs. ...

Page 20

... When the AIE Bit is set to '0,' the AF Bit does not initiate the IRQ signal. The RST pin clears AIE to '0.' The internal functions of the M48T86 do not affect the AIE Bit. ...

Page 21

The 24/12 Control Bit establishes the format of the hours byte. A '1' indicates the 24-hour mode and a '0' indicates the 12-hour mode. This bit is READ/WRITE and is not affected by internal functions or RST. DSE: daylight ...

Page 22

... Register D VRT: valid RAM and time The Valid RAM and Time (VRT) Bit is set to the '1' state by STMicroelectronics prior to shipment. This bit is not writable and should always be a '1' when read '0' is ever present, an exhausted internal lithium cell is indicated and both the contents of the RTC data and RAM data are questionable ...

Page 23

V noise and negative going transients CC I transients, including those produced by output switching, can produce voltage CC fluctuations, resulting in spikes on the V capacitors are used to store energy which stabilizes the V bypass capacitors will be ...

Page 24

... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 9. ...

Page 25

... Input pulse voltages Input and output timing ref. voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC testing load circuit (no IRQ) Parameter ) ) FOR ALL OUTPUTS EXCEPT IRQ 510 M48T86 Unit 4 °C 100 1 ...

Page 26

Figure 13. AC testing load circuit (with IRQ) Table 11. Capacitance Symbol C Input capacitance IN (3) C Input / output capacitance IO 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested 25°C, ...

Page 27

Figure 14. Power down/up mode AC waveforms V CC 4.5V V PFD Table 13. Power down/up mode AC characteristics Symbol Parameter ( fall time rise time ...

Page 28

Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box ...

Page 29

Table 15. PCDIP24 – 24-pin plastic DIP, battery CAPHAT, package mechanical data Symb Typ Figure 16. SOH28 – 28-lead plastic small outline, 4-socket SNAPHAT, package outline B ...

Page 30

Table 16. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package mechanical data Symb Typ 1. Figure 17. SH – 4-pin SNAPHAT housing for 48mAh ...

Page 31

Table 17. SH – 4-pin SNAPHAT housing for 48mAh battery and crystal, package mechanical data Symb Typ Figure 18. SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package ...

Page 32

Table 18. SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package mechanical data Symb Typ 32/36 mm Min Max Typ 10.54 8.00 8.51 7.24 8.00 0.38 0.46 0.56 ...

Page 33

Part numbering Table 19. Ordering information scheme Example: Device Type M48T Supply Voltage and Write Protect Voltage 4.5 to 5.5V Package PC = PCDIP24 ( SOH28 Temperature Range ...

Page 34

Table 20. SNAPHAT battery table Part Number M4T28-BR12SH M4T32-BR12SH 34/36 Description Lithium battery (48mAh) SNAPHAT Lithium battery (120mAh) SNAPHAT Package SH SH ...

Page 35

Revision history Table 21. Document revision history Date Revision Mar-1999 1.0 04-May-2000 1.1 31-Jul-2001 2.0 20-May-2002 2.1 01-Apr-2003 3.0 02-Apr-2004 4.0 20-Feb-2007 5.0 05-Jul-2007 6.0 Changes First Issue Page layout changed Reformatted; temp/voltage info. added to tables Modify reflow time ...

Page 36

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...