m48t86 STMicroelectronics, m48t86 Datasheet - Page 10

• Manufacturer Part Number: m48t86
• Description: 5v Pc Real Time Clock
• Manufacturer: STMicroelectronics

MOT (mode select)
DS (data strobe input)
E (chip enable input)
IRQ (interrupt request output)
RST (reset input)
RCL (RAM clear)
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The MOT pin offers the flexibility to choose between two bus types (see
page
or left disconnected, Intel bus timing is selected. The pin has an internal pull-down
resistance of approximately 20K .
The DS pin is also referred to as READ (RD). A falling edge transition on the Data Strobe
(DS) input enables the output during a a READ cycle. This is very similar to an Output
Enable (G) signal on other memory devices.
The Chip Enable pin must be asserted low for a bus cycle in the M48T86 to be accessed.
Bus cycles which take place without asserting E will latch the addresses present, but no
data access will occur.
The IRQ pin is an open drain output that can be used as an interrupt input to a processor.
The IRQ output remains low as long as the status bit causing the interrupt is present and the
corresponding interrupt-enable bit is set. IRQ returns to a high impedance state whenever
Register C is read. The RST pin can also be used to clear pending interrupts. The IRQ bus
is an open drain output so it requires an external pull-up resistor to V
The M48T86 is reset when the RST input is pulled low. With a valid V
on RST, the following events occur:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Update Ended Interrupt Enable (UIE) is cleared to a zero (Register B; Bit 4).
The RCL pin is used to clear all 114 storage bytes, excluding clock and control registers, of
the array to FF(hex) value. The array will be cleared when the RCL pin is held low for at
least 100ms with the oscillator running. Usage of this pin does not affect battery load. This
function is applicable only when V
Periodic Interrupt Enable (PIE) Bit is cleared to a zero (Register B; Bit 6);
Alarm Interrupt Enable (AIE) Bit is cleared to a zero (Register B; Bit 5);
Update Ended Interrupt Request (UF) Bit is cleared to a zero (Register C; Bit 4);
Interrupt Request (IRQF) Bit is cleared to a zero (Register C Bit 7);
Periodic Interrupt Flag (PF) Bit is cleared to a zero (Register C; Bit 6);
The device is not accessible until RST is returned high;
Alarm Interrupt Flag (AF) Bit is cleared to a zero (Register C; Bit 5);
The IRQ pin is in the high impedance state
Square Wave Output Enable (SQWE) Bit is cleared to zero (Register B; Bit 3); and
12). When connected to V
CC
CC
, Motorola bus timing is selected. When connected to V
is applied.
CC
CC
.
Figure 7 on
applied and a low
SS