m48t86 STMicroelectronics, m48t86 Datasheet - Page 19

• Manufacturer Part Number: m48t86
• Description: 5v Pc Real Time Clock
• Manufacturer: STMicroelectronics

Register A
UIP update in progress
OSC0, OSC1, OSC2 oscillator control
RS3, RS2, RS1, RS0
Table 5.
Figure 9.
BIT7
UIP
UIP
The Update in Progress (UIP) Bit is a status flag that can be monitored. When the UIP Bit is
'1,' the update transfer will soon occur (see
will not occur for at least 244µs. The time, calendar, and alarm information in RAM is fully
available for access when the UIP Bit is '0.' The UIP Bit is “Read only” and is not affected by
RST. Writing the SET Bit in Register B to a '1' inhibits any update transfer and clears the
UIP Status Bit.
These three bits are used to control the oscillator and reset the countdown chain. A pattern
of “010” enables operation by turning on the oscillator and enabling the divider chain. A
pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When “010”
is written, the first update begins after 500ms.
These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the
divider output. The tap selected may be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user may do one of the following:
1.
or
2.
or
3.
or
4.
Table 4 on page 18
may be chosen with the RS Bits. These four READ/WRITE bits are not affected by RST.
Register A MSB
Update period timing and UIP
OSC2
BIT6
Enable the interrupt with the PIE Bit;
Enable the SQW output with the SQWE Bit;
Enable both at the same time and same rate;
Enable neither.
OSC1
BIT5
lists the periodic interrupt rates and the square wave frequencies that
OSC0
BIT4
UPDATE PERIOD (1sec)
Figure
BIT3
RS3
9). When UIP is a '0,' the update transfer
tBUC
BIT2
RS2
tUC
BIT1
RS1
AI01651
BIT0
RS0
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