m48t12 STMicroelectronics, m48t12 Datasheet - Page 9

• Manufacturer Part Number: m48t12
• Description: 5.0v, 16 Kbit 2kb X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

2.2
Figure 5.
Figure 6.
A0-A10
E
W
DQ0-DQ7
A0-A10
E
W
DQ0-DQ7
Write mode
The M48T02/12 is in the WRITE Mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
the end of WRITE and remain valid for t
WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs t
Write enable controlled, write AC waveform
Chip enable controlled, write AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
tAVWH
EHAX
tAVEH
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
WHDX
from Chip Enable or t
afterward. G should be kept high during
tDVEH
tDVWH
DATA INPUT
DATA INPUT
WLQZ
tWHDX
after W falls.
WHAX
tEHDX
tWHQX
from WRITE Enable
tEHAX
tWHAX
AI01332B
AI01331
DVWH
prior to
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