m48t12 STMicroelectronics, m48t12 Datasheet - Page 12

• Manufacturer Part Number: m48t12
• Description: 5.0v, 16 Kbit 2kb X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

3
3.1
3.2
12/24
Clock operations
Reading the clock
Updates to the TIMEKEEPER
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ Bit, the seventh bit in the control
register. As long as a '1' remains in that position, updating is halted. After a halt is issued,
the registers reflect the count; that is, the day, date, and the time that were current at the
moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
Setting the clock
The eighth bit of the control register is the WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with
the correct day, date, and time data in 24 hour BCD format (on
Resetting the WRITE Bit to a '0' then transfers the values of all time registers (7F9-7FF) to
the actual TIMEKEEPER counters and allows normal operation to resume. The FT Bit and
the bits marked as '0' in
TIMEKEEPER and RAM operation.
See the Application Note AN923, “TIMEKEEPER
information on Century Rollover.
Table 5 on page 13
®
registers should be halted before clock data is read to
must be written to '0' to allow for normal
®
Rolling Into the 21
Table 5 on page
st
Century” for
13).