m48t12 STMicroelectronics, m48t12 Datasheet - Page 7

• Manufacturer Part Number: m48t12
• Description: 5.0v, 16 Kbit 2kb X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

2
Note:
2.1
Operation modes
As
oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations
contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made
automatically.
Byte 7F8h is the clock control register. This byte controls user access to the clock
information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T02/12 includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T02/12 also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately 3V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
Table 2.
1. See
X = V
Read mode
The M48T02/12 is in the READ Mode whenever W (WRITE Enable) is high and E (Chip
Enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within Address Access time (t
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the Chip
Enable Access time (t
Deselect
Deselect
Deselect
WRITE
READ
READ
Mode
Figure 3 on page 6
IH
Table 11 on page 20
or V
IL
Operating modes
; V
V
4.75 to 5.5V
4.5 to 5.5V
PFD
≤ V
SO
V
V
SO
or
(min)
SO
CC
= Battery Back-up Switchover Voltage.
to
(1)
ELQV
shows, the static memory array and the quartz controlled clock
(1)
for details.
) or Output Enable Access time (t
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
DQ0-DQ7
High Z
High Z
High Z
High Z
GLQV
D
CC
D
OUT
IN
. As V
).
AVQV
CC
Battery Back-up Mode
) after the last
CC
falls below
CMOS Standby
is out of
Standby
Power
Active
Active
Active
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