pcf2123 NXP Semiconductors, pcf2123 Datasheet - Page 34

• Manufacturer Part Number: pcf2123
• Description: Spi Real Time Clock/calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF2123_1
Product data sheet
9.14 3-line serial interface
Data transfer to and from the device is made via a 3-wire SPI-bus (see
data lines for input and output are split. The data input and output lines can be connected
together to facilitate a bidirectional data bus. The chip enable signal is used to identify the
transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first
(see
Table 41.
The transmission is controlled by the active HIGH chip enable signal CE. The first byte
transmitted is the command byte. Subsequent bytes will be either data to be written or
data to be read. Data is sampled on the rising edge of the clock and transferred internally
on the falling edge.
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
rollover to zero after the last register is accessed. The read/write bit (R/W) defines if the
following bytes will be read or write information.
Symbol
CE
SCL
SDI
SDO
Fig 22. SDI, SDO configurations
Fig 23. Data transfer overview
Figure
Serial interface
chip enable
23).
data bus
Function
chip enable input
serial clock input
serial data input
serial data output
Rev. 01 — 19 November 2008
COMMAND
two wire mode
SDO
SDI
DATA
Description
when LOW, the interface is reset; pull-down resistor
included; active input may be higher than V
may not be wired permanently HIGH
when CE is LOW, this input may float; input may be
higher than V
when CE is LOW, input may float; input may be higher
than V
SCL
push-pull output; drives from V
is changed on the falling edge of SCL; will be high-Z
when not driving; may be connected directly to SDI
DD
single wire mode
SDO
SDI
; input data is sampled on the rising edge of
DATA
DD
001aai560
SPI Real time clock/calendar
DATA
SS
PCF2123
to V
© NXP B.V. 2008. All rights reserved.
Table
001aaf914
DD
; output data
41). The
DD
, but
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