pcf2123 NXP Semiconductors, pcf2123 Datasheet - Page 21

• Manufacturer Part Number: pcf2123
• Description: Spi Real Time Clock/calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF2123_1
Product data sheet
9.8.1 Minute and second interrupt
The minute and second interrupts (bits MI and SI) are pre-defined timers for generating
periodic interrupts. The timers can be enabled independently from one another. However,
a minute interrupt enabled on top of a second interrupt will not be distinguishable since it
will occur at the same time; see
Table 26.
The minute and second flag (bit MSF) is set to logic 1 when either the seconds or the
minutes counter increments according to the currently enabled interrupt. The flag can be
read and cleared by the interface. The status of bit MSF does not affect the INT pulse
generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT
pulse will still be generated.
The purpose of the flag is to allow the controlling system to interrogate the PCF2123 and
identify the source of the interrupt i.e. minute or second, countdown timer or alarm.
Table 27.
Minute interrupt (bit MI)
0
1
0
1
Minute interrupt (bit MI)
0
1
0
1
Fig 14. INT example for MI and SI
MSF when only MI enabled
INT when only MI enabled
MSF when SI enabled
INT when SI enabled
In this example, TI_TP is set to logic 1 resulting in
not cleared after an interrupt.
Effect of bits MI and SI on INT generation
Effect of MI and SI on MSF
seconds counter
minutes counter
Rev. 01 — 19 November 2008
Second interrupt (bit SI)
0
0
1
1
Second interrupt (bit SI)
0
0
1
1
58
Figure
59
14.
59
11
Result
no interrupt generated
an interrupt once per minute
an interrupt once per second
an interrupt once per second
Result
MSF never set
MSF set when minutes counter
increments
MSF set when seconds counter
increments
MSF set when seconds counter
increments
Hz wide interrupt pulse and the MSF flag is
00
12
SPI Real time clock/calendar
00
PCF2123
© NXP B.V. 2008. All rights reserved.
01
001aaf905
21 of 54