pcf2123 NXP Semiconductors, pcf2123 Datasheet - Page 23

• Manufacturer Part Number: pcf2123
• Description: Spi Real Time Clock/calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF2123_1
Product data sheet
If a new value of n is written before the end of the current timer period, then this value will
take immediate effect. NXP does not recommend changing n without first disabling the
counter (by setting bit TE = 0). The update of n is asynchronous to the timer clock,
therefore changing it without setting bit TE = 0 may result in a corrupted value loaded into
the countdown counter which results in an undetermined countdown period for the first
period. The countdown value n will, however, be correctly stored and correctly loaded on
subsequent timer periods.
When the countdown timer flag is set, an interrupt signal on INT will be generated
provided that this mode is enabled. See
be controlled.
When starting the timer for the first time, the first period will have an uncertainty which is a
result of the enable instruction being generated from the interface clock which is
asynchronous from the timer source clock. Subsequent timer periods will have no such
delay. The amount of delay for the first timer period will depend on the chosen source
clock, see
Table 29.
At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF
may only be cleared by software. The asserted bit TF can be used to generate an
interrupt (INT). The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is
used to control this mode selection and the interrupt output may be disabled with bit TIE,
see
When reading the timer, the current countdown value is returned and not the initial
value n. For accurate read back of the countdown value, the SPI-bus clock (SCL) must be
operating at a frequency of at least twice the selected timer clock. Since it is not possible
to freeze the countdown timer counter during read back, it is recommended to read the
register twice and check for consistent results.
Timer source clock frequency selection of 1 Hz and
Offset_register. The duration of a program period will vary according to when the offset is
initiated. For example, if a 100 s timer is set using the 1 Hz clock as source, then some
100 s periods will contain correction pulses and therefor be longer or shorter depending
on the setting of the Offset_register. See
Offset_register.
Timer source clock
4.096 kHz
64 Hz
1 Hz
1
60
Hz
Table
6.
Table
First period delay for timer counter value n
29.
Rev. 01 — 19 November 2008
Minimum timer period
n
n
(n
(n
1) +
1) +
1
1
64
64
Section 9.9.2
Section 9.11
Hz
Hz
1
60
for details on how the interrupt can
to understand the operation of the
Hz will be affected by the
SPI Real time clock/calendar
Maximum timer period
n + 1
n + 1
n +
n +
1
1
64
64
Hz
Hz
PCF2123
© NXP B.V. 2008. All rights reserved.
23 of 54