hsp43168 Intersil Corporation, hsp43168 Datasheet - Page 6

• Manufacturer Part Number: hsp43168
• Description: Dual Fir Filter
• Manufacturer: Intersil Corporation

Functional Description
As shown in Figure 1, the HSP43168 consists of two
4-multiplier FIR filter cells which process 10-bit data and
coefficients. The FIR cells can operate as two independent
8-tap FIR filters or two 4-tap asymmetric filters at maximum
I/O rates. A single filter mode is provided which allows the
FIR cells to operate as one 16-tap FIR filter or one 8-tap
asymmetric filter. On board coefficient storage for up to 32
sets of 8 coefficients is provided. The coefficient sets are
user selectable and are programmed through a
microprocessor interface. Programmable decimation to 16 is
also provided. By utilizing Decimation Registers together
with the coefficient sets, polyphase filters are realizable
which allow the user to trade data rate for filter taps. The
MUX/Adder can be configured to either add or multiplex the
outputs of the filter cells depending upon whether the cells
are operating in single or dual filter mode. In addition, a
shifter in the MUX/Adder is provided for implementation of
filters with 10-bit data and 20-bit coefficients or vice versa.
Preparing the Dual FIR for Operation
Two configuration steps are required to prepare the Dual FIR
Filter for normal operation: 1) loading the Configuration
Control Registers, and 2) loading the FIR Filter Coefficients.
Configuration Control Registers are loaded by placing the
control register address on address lines A0-8, placing the
configuration data on the configuration input lines CIN0-9,
and asserting the WR line (followed by a release of the
assertion). This action creates a rising edge on the WR line,
which clocks the address and configuration data into the part.
The details of the “Load Configuration” process are outlined in
“Microprocessor Interface” on page 6.
FIR Coefficients are loaded by placing the address of the
Coefficient Data Bank on the address lines A0-8, placing
the FIR 10-bit coefficient values on the configuration input
lines CIN0-9 and then asserting the WR line (followed by a
release of the assertion). This action creates a rising edge
on the WR line, which clocks the FIR Coefficient Band
address and FIR Coefficient data into the part. The details
of the “Load FIR Coefficient” process are outlined in
“Coefficient Bank” on page 8.
Both the Configuration Load and FIR Coefficient Load can
be done as a sequence of asynchronous write commands
to the Dual FIR Filter. Once these actions are complete, the
part is ready for normal filter operation. The CLK, TXFR,
FWRD, RVRS, ACCEN, and SHFTEN signals must be
asserted in a manner determined by the application.
MUX0-1 must meet the setup and hold times with respect
to clock for proper filter operation. Details of the MUX1-0
control can be found in “Output MUX/Adder” on page 9.
Details of the ACCEN control can be found in “FIR Cell
Accumulator” on page 9. Bit locations for the various filter
control/configuration signals can be found in “Input/Output
Formats” on page 10.
6
HSP43168
The Dual FIR Filter has a “pipeline” delay of 8 CLK periods,
once normal filtering operations begin. Five typical filtering
operation examples are provided in “Application Examples”
on page 10 as a guide to configuration and control of the
Dual FIR Filter.
During normal filter operations, the location and duration of
the TXFR signal assertions are determined by the filter
configuration and operation mode. Once set, these signal
parameters must be maintained during normal operation to
ensure proper data alignment in the part. Once the part is
reset, do not change TXFR unless you load the configuration
again.
NOTE: The fixed or periodic relationship between the
TXFR signal and CLK must be maintained for valid filter
operation. This relationship can only change when CLK
is halted and new configuration control words are
loaded into the device.
Microprocessor Interface
The Dual FIR has a 20 pin write only microprocessor interface
for loading data into the Control Block and Coefficient Banks.
The interface consists of a 10-bit data bus (CIN0-9), a 9-bit
address bus (A0-8), and a write input (WR) to latch the data
into the on-board registers on a rising edge. The configuration
control and coefficient data loading is asynchronous to CLK.
Control Block
The Dual FIR is configured by writing to the registers within
the Control Block. Figure 2 shows the timing diagram for
writing to the Configuration Control Registers. These Control
Registers are memory mapped to Address 000H (H =
Hexadecimal) and 001H on A0-8. The Filter Coefficient
Registers are mapped to 1XXH (X = value described in
“Coefficient Bank” on page 8).
The format of the Control Registers is shown in Table 1 and
Table 2. Writing to any of the Control/Configuration Registers
causes a reset which lasts for 6 CLK cycles following the
assertion of WR. The reset caused by Writing Registers in
the Control Block will not clear the contents of the Coefficient
Bank. As shown in Figure 2, either Configuration Control
Register can be written to during reset.
FIGURE 2. LATCHING C9-0 VALUES INTO ADDRESS A8-0
RESET
C9-0
A8-0
WR
REGISTERS
000H
001H