hsp43168 Intersil Corporation, hsp43168 Datasheet - Page 11

• Manufacturer Part Number: hsp43168
• Description: Dual Fir Filter
• Manufacturer: Intersil Corporation

configuration unique parameters, while Register 001H, bit 4, is
filter configuration unique. Table 7 details the configuration
control register values, the number of filter coefficient banks
required and the MUX1-0 control values for each filter example.
Example 1. Even-Tap Even Symmetric Filter
Example
The HSP43168 may be configured as two independent
8-tap symmetric filters as shown by the Block Diagram in
Figure 5. Each of the FIR cells takes advantage of
symmetric filter coefficients by pre-adding data samples
common to a given coefficient. As a result, each FIR cell
can implement an 8-tap symmetric filter using only four
multipliers. Similarly, when the HSP43168 is configured in
single filter mode a 16-tap symmetric filter is possible by
using the multipliers in both cells.
The operation of the FIR cell is better understood by comparing
the data and coefficient alignment for a given filter output,
Figure 6, with the data flow through the FIR cell, as shown in
Figure 7. The Block Diagrams in Figure 7 are a simplification of
the FIR cell shown in Figure 1. For simplicity, the ALUs and FIR
Cell Accumulators were replaced by adders, and the Pipeline
Delay Registers were omitted. In this example, we will only
show the data flow through one of the two FIR cells.
In Figure 7, the order of the data samples within the filter
cell is shown by the numbers in the forward and backward
given by the equation at the bottom of each block diagram.
Figure 7A shows the data sample alignment at the pre-
adders for the data/coefficient alignment shown in Figure 6.
shifting decimation paths. The output of the filter cell is
FIGURE 5. USING HSP43168 AS TWO INDEPENDENT FILTERS
Even Tap Even
Symmetric
Odd Tap Even Symmetric
Asymmetric
Even Tap Decimate by
N+1
Odd Tap Decimate by
N+1
Dual: Even and Odd Tap
Decimate by N+1
TABLE 7. CONFIGURATION CONTROL REGISTER VALUES
INA0-9
INB0-9
A
B
FILTER TYPE
A
B
8-TAP EVEN SYMMETRIC
8-TAP EVEN SYMMETRIC
FIR A
FIR B
15N or
REG
HEX
1dN
11N
19N
110
000
1d0
110
HSP43168
11
REG
HEX
Bit 4
001
010
010
010
000
000
000
M
COEFFICIENT
U
X
# OF FILTER
BANKS
N+1
N+1
N+1
1
1
2
OUT9-27
10 and
MUX
1-0
10
10
10
10
10
11
HSP43168
The dual filter application is configured by writing 1d0H to
address 000H via the microprocessor interface, CIN0-9, A0-8,
and WR. Since this application does not use decimation, the
4th bit of the Control Register at Address 001H must be set to
disable data reversal (see Table 2). Failure to disable data
reversal will produce erroneous results.
Using this architecture, only the unique coefficients need to
be stored in the Coefficient Bank. For example, the above
filter would be stored in the first coefficient set for FIR A by
writing C0, C1, C2, and C3 to Address 100H, 101H, 102H,
and 103H respectively. To write the same filter to the first
coefficient set for FIR B, the address sequence would
change to 104H, 105H, 106H, and 107H.
To operate the HSP43168 in this mode, TXFR is tied low to
ensure proper data flow; both FWRD and RVRS are tied low
to enable data samples from the forward and reverse data
paths to the ALUs for pre-adding; ACCEN is tied low to
prevent accumulation over multiple CLKs; SHFTEN is tied low
to allow shifting of data through the Decimation Registers;
MUX0-1 is programmed to multiplex the output the of either
FIR A or FIR B; CSEL0-4 is programmable to access the
stored coefficient set, in this example CSEL = 00000.
FIGURE 7A. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED
h(n)
x(n)
FIGURE 6. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP
C0
7
(X7 + X0)C0 + (X6 + X1)C1 + (X5 + X2)C2 + (X4 + X3)C3
X9
+
EVEN SYMMETRIC FILTER
INTO THE FEED FORWARD STAGE
X8
C1
0
6
C0
X7
+
C1
X6
C2
1
5
+
C2
X5
+
C3
X4
C3
2
4
C3
X3
+
C2
X2
3
C1
X1
8 TAPS
C0
X0