hsp43168 Intersil Corporation, hsp43168 Datasheet - Page 15

• Manufacturer Part Number: hsp43168
• Description: Dual Fir Filter
• Manufacturer: Intersil Corporation

†Note that CLK is 2X data rate.
Example 4. Even-Tap Decimating Filter Example
The HSP43168 supports filtering applications requiring
decimation to 16. In these applications the output data rate is
reduced by a factor of N. As a result, N clock cycles can be
used for the computation of the filter output. For example,
each FIR cell can calculate 8 symmetric or 4 asymmetric
taps in one clock. If the application requires decimation by
two, the filter output can be calculated over two clocks thus,
boosting the number of taps per FIR cell to 16 symmetric or
8 asymmetric. For this example, each FIR cell is configured
as an independent 24-tap decimate x3 filter. Again, the data
flow diagrams show only one of the FIR cells shown in
Figure 15.
CSEL0-4
SHFTEN
ACCEN
FIGURE 14. CONTROL TIMING FOR 8-TAP ASYMMETRIC
INA0-9
FIGURE 15. EVEN-TAP DECIMATING FILTER, 24-TAP DEC = 3
FWRD
CLK
RVRS
TXFR
INA0-9
INB0-9
A
B
†
A
B
1
FILTER
X0
0
EVEN-TAP DECIMATING
EVEN-TAP DECIMATING
0
1
1
FIR A
FIR B
X1
2
(TIED LOW)
HSP43168
0
15
3
X6
0
13
M
U
X
1
X7
14
0
15
1
OUT9-27
X8
16
0
HSP43168
h(n)
C0
x(n)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
FIGURE 16. DATA/COEFFICIENT ALIGNMENT FOR 24-TAP
C1
The alignment of data relative to the 24 filter coefficients for
a particular output is depicted graphically in Figure 16. As in
previous examples, the HSP43168 implements the filtering
operation by summing data samples prior to multiplication by
the common coefficient. In this example an output is required
every third CLK which allows 3 CLKs for computation. On
each CLK, one of three sets of coefficients are used to
calculate 8 of the filter taps. The Block Diagrams in Figure 17
show the data flow and accumulator output for the
data/coefficient alignment in Figure 16.
Proper data and coefficient alignment is achieved by
asserting TXFR once every three CLKs to switch the LIFOs
which are being read and written. This has the effect of
feeding blocks of three samples into the backward shifting
decimation path which are reversed in sample order. In
addition, ACCEN is deasserted once every three clocks to
allow accumulation over three CLKs. The three sets of
coefficients required in the calculation of a 24-tap symmetric
filter are cycled through using CSEL0-4. The timing
relationship between the CSEL0-4, ACCEN, and TXFR are
shown in Figure 18.
To operate in this mode the Dual is configured by writing 1d2
to Address 000H via the microprocessor interface, CIN0-9,
A0-8, and WR. Data reversal must be enabled see (Table 2).
The 12 unique coefficients for this example are stored as
three sets of coefficients for either FIR cell. For FIR A, the
coefficients are loaded into the Coefficient Bank by writing
C2, C5, C8, C11, C1, C4, C7, C10, C0, C3, C6, and C9 to
Address [100H, 101H, 102H, 103H], CSEL = 0; [108H,
109H, 10aH, 10bH], CSEL = 1; [110H, 111H, 112H, and
113H], CSEL = 2, respectively.
C2
C3
C4
C5
DECIMATE BY 3 FIR FILTER
C6
C7
C8
C9
C10
C11
C11
C10
C9
C8
8 7
C7 C6
6 5
C5
C4 C3
4
3 2
C2
24-TAPS
C1
1
C0
0