hsp43168 Intersil Corporation, hsp43168 Datasheet
hsp43168
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hsp43168 Summary of contents
Page 1
... Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface. ...
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... INA INA 4 INA 3 INA 2 INA 1 INA 0 INB 9 2 HSP43168 COEFFICIENT BANK A FIR CELL A MUX MUX MUX / ADDER 9 HSP43168 84 LD PLCC TOP VIEW ...
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... CIN3 CIN2 CIN1 CIN0 INA9 INA8 INA7 INA6 INA5 INA4 INA3 INA2 INA1 INA0 NC NC INB9 INB8 INB7 3 HSP43168 HSP43168 100 LD MQFP TOP VIEW 100 ...
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... Output Enable High. This three-state control enables OUT9-27 when OEH is low. ACCEN I Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the Accumulator. 4 HSP43168 DESCRIPTION ...
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TXFR DELAY 4 DELAY 3 FIR A REVERSE PATH DECIMATION REGISTERS FIR A FORWARD PATH DELAY 1-16 †† SHFTEN DELAY 3 10 DELAY INA0-9 DELAY 3 †† 1-16 M DELAY 3 U INB0 INB1- ...
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... Functional Description As shown in Figure 1, the HSP43168 consists of two 4-multiplier FIR filter cells which process 10-bit data and coefficients. The FIR cells can operate as two independent 8-tap FIR filters or two 4-tap asymmetric filters at maximum I/O rates. A single filter mode is provided which allows the FIR cells to operate as one 16-tap FIR filter or one 8-tap asymmetric filter ...
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... FIR cells operate as two independent filters or one extended length filter. Dual filter mode assumes Filter A 7 HSP43168 and Filter B are separate independent filters. In the single filter mode, the data is routed through the forward paths of Filters A and B before entering the reverse paths of Filters A and B (see Figure 1) ...
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... Data Feedback Circuitry in FIR B. Thus, the manner in which data is read into the reverse decimation 8 HSP43168 path is determined by FIR B's configuration. When the decimation paths are cascaded, data is routed through the fourth delay stage in FIR A's forward path to FIR B. ...
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... Output Holding Registers. When ACCEN is asserted, accumulation is enabled and the contents of the Output Holding Registers remain unchanged. 9 HSP43168 Output MUX/Adder The contents of each FIR Cell's Output Holding Register is summed or multiplexed in the Mux/Adder. The operation of the Mux/Adder is controlled by the MUX1-0 inputs as shown in Table 5 ...
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... In this section a number of examples are presented which detail even, odd, symmetric, asymmetric, decimating and dual FIR filter configurations. These examples are intended to illustrate the different operational features of the HSP43168 and should be used as a guide in developing an -16 -17 -18 application specific filter configuration. Use Table 6 to select and find the example that best matches your application ...
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... FIR B, the address sequence would change to 104H, 105H, 106H, and 107H. To operate the HSP43168 in this mode, TXFR is tied low to ensure proper data flow; both FWRD and RVRS are tied low to enable data samples from the forward and reverse data paths to the ALUs for pre-adding ...
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... INA0 7-TAP EVEN SYMMETRIC B B INB0-9 FIR B FIGURE 8. USING HSP43168 AS TWO INDEPENDENT FILTERS 12 HSP43168 The operation of the FIR cell for odd length filters is better 3 4 understood by comparing the data/coefficient alignment in Figure 9 with the Data Flow Diagrams in Figure 10. The Block Diagrams in Figure 10 are a simplification of the FIR 5 cell shown in Figure 1 ...
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... The control signals TXFR, FWRD, RVRS, ACCEN, SHFTEN, and CSEL0-4 are controlled as described in Example 1. Example 3. Asymmetric Filter Example The FIR cells within the HSP43168 can each calculate 4 asymmetric taps on each clock. Thus, a single FIR cell can implement an 8-tap asymmetric filter if the HSP43168 is clocked at twice the input data rate ...
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... C5, and C4 to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, and 10bH respectively. The sum of products required for this 8-tap filter require dynamic control over FWRD, RVRS, ACCEN, and CSEL0-4. The relative timing of these signals is shown in Figure 14. 14 HSP43168 FIGURE 13B ...
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... FIGURE 15. EVEN-TAP DECIMATING FILTER, 24-TAP DEC = 3 15 HSP43168 The alignment of data relative to the 24 filter coefficients for particular output is depicted graphically in Figure 16 previous examples, the HSP43168 implements the filtering operation by summing data samples prior to multiplication the common coefficient. In this example an output is required every third CLK which allows 3 CLKs for computation ...
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... X24)C0 + (X8 + X21)C5 + (X11 + X18)C8 + (X14 + X15)C11 FIGURE 17D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS Example 5. Odd-Tap Decimating Symmetric Filter This example highlights the use of the HSP43168 as two independent, 23-tap, symmetric, decimate by 3 filters. In this example, the operational differences in the control signals and data reversal structure may be compared to the previously discussed even-tap decimating filter ...
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... CLOCKED INTO THE FEED FORWARD STAGE FIGURE 20. DATA FLOW DIAGRAMS FOR 23-TAP DECIMATE BY 3 SYMMETRIC FILTER 17 HSP43168 Proper data and coefficient alignment is achieved by asserting TXFR once every three CLKs to switch the LIFOs which are being read and written. In the odd-tap mode, TXFR is internally delayed by one clock cycle with respect to ACCEN so that the convolutional sum will be computed correctly ...
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... HSP43168 Example 6. Dual Decimation Example 23-TAPS The purpose of this example is to give an overview of one of C6 the more complex applications of the HSP43168. The input two data streams (A) and (B) samples. Figure 23 shows the upper level block diagram of the system being implemented ...
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... C5 C8 ACCUMULATOR (X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11 FIGURE 26A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED FORWARD STAGE 19 HSP43168 Figure 25 shows the Timing Diagram required to obtained the 23-TAPS FIRB multiplexed/decimated output. The output of the two filters are D8 D7 provided at by selecting the odd-decimation filter first, then the ...
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... X23)C0 + (X3 + X20)C3 + (X6 + X17)C6 + (X9 + X14)C9 + (X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10 + (X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11 FIGURE 26C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 26. DATA FLOW DIAGRAM FOR MULTIPLEXED DECIMATION EXAMPLE 20 HSP43168 FIR ...
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... Power Supply current is proportional to operating frequency. Typical rating for I 6. Output load per test load circuit and C 7. Maximum junction temperature must be considered when operating part at high clock frequencies. 21 HSP43168 Thermal Information Thermal Resistance (Typical, Note +0.5V MQFP Package ...
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... Setup time requirement for loading of data on CIN0-9 to guarantee recognition on the following clock. 10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. 22 HSP43168 ° = +4.75V to +5.25V 0°C to +70 C Commercial ...
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... Waveforms CLK CSEL0 - 4, MUX0 - 1 SHFTEN, FWRD RVRS, TXFR INA0 - 9, INB0 - 9, ACCEN OUT0 - CIN0 - 9 OEL, OEH OUT0 - 27 23 HSP43168 ECS ECH WLCL AWH AWS t t CWS CWH t CVCL 1.5V 1. 1.7V 1.3V HIGH IMPEDANCE FIGURE 27. OUTPUT ENABLE, DISABLE TIMING 2 ...
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... MIN 0.008 o 0 MIN 0.13/0.17 0.005/0.007 -16 L BASE METAL 24 HSP43168 Q100.14x20 100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL -B- e SEATING PLANE A 0.076 0.003 NOTES: -C- 1. Controlling dimension: MILLIMETER. Converted inch All dimensions and tolerances per ANSI Y14.5M-1982. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 HSP43168 N84.1.15 0.004 (0.10 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0 ...