hsp43168 Intersil Corporation, hsp43168 Datasheet - Page 10

• Manufacturer Part Number: hsp43168
• Description: Dual Fir Filter
• Manufacturer: Intersil Corporation

-2
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
2
Input/Output Formats
The Dual FIR supports mixed mode arithmetic with both
unsigned and two's complement data and coefficients. The
input and output formats for both data types are shown below.
If the Dual FIR is configured as an even symmetric filter with
unsigned data and coefficients, the output will be unsigned.
Otherwise, the output will be two's complement.
The MUX/Adder can be configured to implement
programmable rounding at bit locations 2-10 through 21. The
round is implemented by adding a 1 to the specified location
(see Table 2). Figure 4 illustrates the rounding operation. For
example, to configure the part such that the output is
rounded to the 10 MSBs, OUT18 - 27, the round position
would be chosen to be 2-1. The negative sign on the MSB
indicates 2’s complement format.
9
9
-2
2
9
2
9
2
0
0
8
8
2
2
-10
-10
8
8
2
2
FIGURE 3. INPUT/OUTPUT FORMAT DEFINITIONS
7
7
.2
.2
8
8
-1
-1
2
2
6
2
6
2
-11
-11
7
7
INPUT DATA FORMAT INA0-9, INB0-9
INPUT DATA FORMAT INA0-9, INB0-9
2
2
FRACTIONAL TWO’S COMPLEMENT
FRACTIONAL TWO'S COMPLEMENT
5
5
2
FRACTIONAL TWO'S COMPLEMENT
2
7
OUTPUT DATA FORMAT OUT0-8
7
OUTPUT DATA FORMAT OUT0-8
OUTPUT DATA FORMAT OUT9-27
-2
-2
OUTPUT DATA FORMAT OUT9-27
2
2
2
2
4
4
-12
-12
6
6
FRACTIONAL UNSIGNED
FRACTIONAL UNSIGNED
FRACTIONAL UNSIGNED
2
2
2
2
3
3
6
6
-3
-3
2
2
2
2
-13
-13
2
5
2
5
2
2
2
2
5
5
-4
1
-4
1
2
2
10
2
2
-14
-14
4
4
0
0
2
2
.2
.2
4
4
-5
-5
-1
-1
2
2
-15
-15
2
2
3
3
-2
-2
2
2
3
3
2
2
-6
-6
-3
-3
2
2
-16
-16
2
2
2
2
-4
-4
2
2
2
2
-7
-7
2
2
2
2
-5
-5
-17
-17
1
1
2
2
2
-6
2
-6
1
1
-8
-8
2
2
2
2
-7
-7
-18
-18
0
0
2
2
2
2
0
-8
0
-8
-9
-9
HSP43168
2
2
-9
-9
Application Examples
In this section a number of examples are presented which
detail even, odd, symmetric, asymmetric, decimating and
dual FIR filter configurations. These examples are intended
to illustrate the different operational features of the
HSP43168 and should be used as a guide in developing an
application specific filter configuration. Use Table 6 to select
and find the example that best matches your application.
Examples 1 through 5 are explained using a single four tap
FIR cell, but the same concept applies to FIR filters which
use both FIR cells (A and B) in a single filter configuration.
Example 6 details a dual filter mode where FIR cell A and B
implement different digital filters. All examples are
functionally verified configurations. Each example details a
complete design solution, including a block diagram, a
data/coefficient alignment illustration, a data flow diagram
and a control signal timing diagram.
Two programmable Configuration Control Registers define a
unique FIR filter configuration. Register 000H has all filter
Even Tap Even Symmetric
Odd Tap Even Symmetric
Asymmetric
Even Tap Decimating
Odd Tap Decimating
Dual Decimating
I
I
9-27
OUT
OUT
0-8
TABLE 6. FILTER EXAMPLE SELECTION GUIDE
FIGURE 4. ROUND POSITION BIT DEFINITION
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FILTER TYPE
OUTPUT BITS
2
2
2
2
2
2
2
2
2
2
2
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
LOCATION OF ADDITION OF 1
10
12
13
14
15
16
17
18
19
11
8
9
NUMBER OF OUTPUT BITS
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
“ROUND POSITION” VALUE
EXAMPLE NUMBER
1
2
3
4
5
6