adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 24

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

ADF4351
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantiza-
tion noise of the SDM also depends on the particular phase
word with which the modulator is seeded.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
look-up table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4351.
If a look-up table is not used, keep the phase word at a constant
value to ensure consistent spur levels on any particular frequency.
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of the
MOD phase offsets with respect to the input reference, where
MOD is the fractional modulus. The phase resync feature in the
ADF4351 produces a consistent output phase offset with respect
to the input reference. This is necessary in applications where the
output phase and frequency are important, such as digital beam
forming. See the Phase Programmability section to program a
specific RF output phase when using phase resync.
Phase resync is enabled by setting Bits [DB16:DB15] in
Register 3 to 1, 0. When phase resync is enabled, an internal
timer generates sync signals at intervals of t
following formula:
where:
t
CLK_DIV_VALUE is the decimal value programmed in
Bits [DB14:DB3] of Register 3 and can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bits [DB14:DB3] of
Register 1 (R1).
PFD
is the PFD reference period.
t
SYNC
= CLK_DIV_VALUE × MOD × t
PFD
SYNC
given by the
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When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The t
a value that is as least as long as the worst-case lock time. This
guarantees the phase resync occurs after the last cycle slip in the
PLL settling transient.
In the example shown in Figure , the PFD reference is 25 MHz and
MOD = 125 for a 200 kHz channel spacing. t
by programming CLK_DIV_VALUE = 80.
Phase Programmability
The phase word in Register 1 controls the RF output phase. As
this word is swept from 0 to MOD, the RF output phase sweeps
over a 360° range in steps of 360°/MOD.
FREQUENCY
(INTERNAL)
PHASE
SYNC
LE
–100
LAST CYCLE SLIP
0
Figure 33. Phase Resync Example
Preliminary Technical Data
100
200
SYNC
INCORRECT PHASE
300
PLL SETTLES TO
t
SYNC
time is to be programmed to
400
TIME (µs)
500
600
SYNC
CORRECT PHASE
PLL SETTLES TO
AFTER RESYNC
700
is set to 400 µs
800
900
1000