adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 14

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

ADF4351
REGISTER MAPS
1
2
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.
0
0
0
0
0
0
RESERVED
N16
L2
0
0
0
0
NOISE
MODE
N15
L1
0
0
0
0
RESERVED
PH1
RESERVED
N14
M3
0
0
0
MUXOUT
RESERVED
N13
M2
P1
0
0
0
N12
P12
M1
0
0
0
16-BIT INTEGER VALUE (INT)
RD2
N11
P11
0
0
0
N10
RD1
P10
0
0
0
12-BIT PHASE VALUE (PHASE)
D15
R10
BS1
D13
N9
P9
LD PIN
MODE
D14
D12
R9
N8
P8
F3
DIVIDER
SELECT
DBB 2
D11
N7
P7
R8
F2
0
RESERVED
RESERVED
D10
N6
P6
R7
V2
1
10-BIT R COUNTER
N5
P5
R6
V1
0
1
Figure 23. Register Summary
N4
R5
P4
F1
0
0
Rev. PrC | Page 14 of 28
DBR
N3
P3
R4
0
0
0
1
REGISTER 5
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
R3
C2
N2
P2
0
0
MODE
DBR
CLK
DIV
RESERVED
1
N1
R2
C1
P1
0
0
M12
D12
F12
R1
0
0
M11
D11
F11
D1
0
0
M10
CP4
F10
D10
0
0
12-BIT FRACTIONAL VALUE (FRAC)
CURRENT
SETTING
12-BIT MODULUS VALUE (MOD)
CP3
RESERVED
M9
F9
D9
0
0
12-BIT CLOCK DIVIDER VALUE
CP2
M8
F8
D8
D8
0
Preliminary Technical Data
DBR
CP1
M7
F7
D7
D7
0
1
RESERVED
M6
F6
U6
D6
D6
0
M5
U5
D5
F5
D5
0
M4
F4
U4
D4
D4
0
DBR 1
M3
U3
D3
D3
F3
0
OUTPUT
M2
U2
F2
D2
D2
POWER
0
M1 C3(0) C2(0) C1(1)
U1
D1
F1
D1
0
C3(1) C2(0) C1(1)
C3(0) C2(0) C1(0)
C3(0) C2(1) C1(0)
C3(0) C2(1) C1(1)
C3(1) C2(0) C1(0)
DB2
DB2
DB2
DB2
DB2
DB2
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
BITS
BITS
BITS
BITS
BITS
BITS
DB1
DB1
DB1
DB1
DB1
DB1
DB0
DB0
DB0
DB0
DB0
DB0