adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 19

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
synthesizer. When the doubler is enabled, both the rising and
falling edges of REF
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to
the REF
much as 5 dB for the REF
range. The phase noise is insensitive to the REF
in the lowest noise mode and when the doubler is disabled.
The maximum allowable REF
is enabled is 30 MHz.
RDIV2
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and PFD, which extends the maximum
REF
to appear at the PFD input, which is necessary for cycle slip
reduction.
10–Bit R Counter
The 10–bit R counter allows the input reference frequency
(REF
to the PFD. Division ratios from 1 to 1023 are allowed.
Double Buffer
DB13 enables or disables double buffering of Bits [DB22:DB20]
in Register 4. The Divider Select section explains how double
buffering works.
Charge Pump Current Setting
Bits [DB12:DB09] set the charge pump current setting. This
should be set to the charge pump current that the loop filter
is designed with (see Figure ).
LDF
Setting DB8 to 1 enables integer–N digital lock detect,
when the FRAC part of the divider is 0; setting DB8 to 0
enables fractional–N digital lock detect.
IN
IN
input rate. This function allows a 50% duty cycle signal
) to be divided down to produce the reference clock
IN
duty cycle. The phase noise degradation can be as
IN
become active edges at the PFD input.
IN
duty cycles outside a 45% to 55%
IN
frequency when the doubler
IN
duty cycle
Rev. PrC | Page 19 of 28
Lock Detect Precision (LDP)
When DB7 is set to 0, 40 consecutive PFD cycles of 10 ns must
occur before digital lock detect is set. When this bit is programmed
to 1, 40 consecutive reference cycles of 6 ns must occur before
digital lock detect is set. This refers to fractional-N digital lock
detect (set DB8 to 0). With integer–N digital lock detect activated
(set DB8 to 1), and DB7 set to 0, then five consecutive cycles of
6 ns need to occur before digital lock detect is set. When DB7 is
set to 1, five consecutive cycles of 10 ns must occur.
Phase Detector Polarity
DB6 sets the phase detector polarity. When a passive loop filter,
or noninverting active loop filter is used, this should be set to 1.
If an active filter with an inverting characteristic is used, it
should be set to 0.
Power-Down
DB5 provides the programmable power-down mode. Setting this
bit to 1 performs a power-down. Setting this bit to 0 returns the
synthesizer to normal operation. When in software power-down
mode, the part retains all information in its registers. Only if the
supply voltages are removed are the register contents lost.
When a power-down is activated, the following events occur:
•
•
•
•
•
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Charge Pump Three-State
DB4 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
Counter Reset
DB3 is the R counter and N counter reset bit for the ADF4351.
When this is 1, the RF synthesizer N counter and R counter are
held in reset. For normal operation, this bit should be set to 0.
The synthesizer counters are forced to their load state
conditions.
The VCO is powered down.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF
The input register remains active and capable of loading
and latching data.
OUT
buffers are disabled.
ADF4351