adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 20

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

ADF4351
REGISTER 3
Control Bits
With Bits [C3:C1] set to 0, 1, 1, Register 3 is programmed.
Figure shows the input data format for programming this
register.
Band Select Clock Mode
Setting DB23 bit to 1 selects a faster logic sequence of band
select, suitable for high PFD frequencies, which is necessary for
fastlock applications. Setting this bit to 0 is recommended for
low PFD values.
Anti-backlash pulse width
Setting DB22 bit to 0 sets the PFD anti-backlash pulse width to
6 ns. This is the recommended mode for fractional-N use.
Setting this bit to 1, the 3 ns pulse-width is used and will result
in a phase noise and spur improvement in integer-N operation.
For fractional-N mode it is not recommended to use this
smaller setting.
Charge cancellation mode pulse width
Setting this bit to 1 enables charge pump charge cancellation.
This has the effect of reducing PFD spurs in Integer-N mode. In
fractional-N mode this should not be used and the relevant
result in a phase noise and spur improvement. For fractional-N
mode it is not recommended to use this smaller setting.
CSR Enable
Setting DB18 to 1 enables cycle slip reduction. This is a method
for improving lock times. Note that the signal at the phase fre-
quency detector (PFD) must have a 50% duty cycle for cycle slip
reduction to work. The charge pump current setting must also
be set to a minimum. See the Cycle Slip Reduction for Faster
Lock Times section for more information.
Clock Divider Mode
Bits [DB16:DB15] must be set to 1, 0 to activate PHASE resync
or 0, 1 to activate fast lock. Setting Bits [DB16:DB15] to 0, 0
disables the clock divider. See Figure .
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of PHASE resync. See the Phase Resync section for
more information. It also sets the timeout counter for fast lock.
See the Fast-Lock Timer and Register Sequences section for
more information.
REGISTER 4
Control Bits
With Bits [C3:C1] set to 1, 0, 0, Register 4 is programmed.
Figure shows the input data format for programming this
register.
Feedback Select
DB23 selects the feedback from the VCO output to the
N counter. When set to 1, the signal is taken from the VCO
directly. When set to 0, it is taken from the output of the output
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dividers. The dividers enable covering of the wide frequency band
(34.375 MHz to 4.4 GHz). When the divider is enabled and the
feedback signal is taken from the output, the RF output signals
of two separately configured PLLs are in phase. This is useful in
some applications where the positive interference of signals is
required to increase the power.
Divider Select
Bits [DB22:DB20] select the value of the output divider (see
Figure ).
Band Select Clock Divider Value
Bits [DB19:DB12] set a divider for the band select logic
clock input. The output of the R counter, is by default, the
value used to clock the band select logic, but, if this value is
too high (>125 kHz), a divider can be switched on to divide
the R counter output to a smaller value (see Figure ).
VCO Power-Down
DB11 powers the VCO down or up depending on the chosen value.
Mute Till Lock Detect
If DB10 is set to 1, the supply current to the RF output stage is shut
down until the part achieves lock as measured by the digital lock
detect circuitry.
AUX Output Select
DB9 sets the auxiliary RF output. The selection can be either
the output of the RF dividers or fundamental VCO frequency.
AUX Output Enable
DB8 enables or disables auxiliary RF output, depending on the
chosen value.
AUX Output Power
Bits [DB7:DB6] set the value of the auxiliary RF output power
level (see Figure ).
RF Output Enable
DB5 enables or disables primary RF output, depending on the
chosen value.
Output Power
Bits [DB4:DB3] set the value of the primary RF output power
level (see Figure ).
REGISTER 5
Control Bits
With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed.
Figure shows the input data form for programming this
register.
Lock Detect Pin Operation
Bits [DB23:DB22] set the operation of the lock detect pin (see
Figure ).
Preliminary Technical Data