gtlp36t612 Fairchild Semiconductor, gtlp36t612 Datasheet

gtlp36t612

Manufacturer Part Number

gtlp36t612

Description

36-bit Lvttl/gtlp Universal Bus Transceiver

Manufacturer

Fairchild Semiconductor

Datasheet

1.GTLP36T612.pdf (8 pages)

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GTLP36T612G

(Note 1)(Note 2)

GTLP36T612

36-Bit LVTTL/GTLP Universal Bus Transceiver

General Description

The GTLP36T612 is an 36-bit universal bus transceiver

which provides LVTTL to GTLP signal level translation. It

allows for transparent, latched and clocked modes of data

transfer. The device provides a high speed interface for

cards operating at LVTTL logic levels and a backplane

operating at GTLP logic levels. High speed backplane

operation is a direct result of GTLP’s reduced output swing

( 1V), reduced input threshold levels and output edge rate

control. The edge rate control minimizes bus settling time.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different output

levels and receiver thresholds. GTLP output LOW level is

less than 0.5V, the output HIGH is 1.5V and the receiver

threshold is 1.0V.

Ordering Code:

Note 1: Ordering code “G” indicates Trays.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package Number

BGA114A

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

DS500590

Features

Bidirectional interface between GTLP and LVTTL logic

levels

Designed with edge rate control circuitry to reduce out-

put noise on the GTLP port

Partitioned as two 18-Bit transceivers with individual

latch timing and output control

receiver threshold adjustibility

Special PVT compensation circuitry to provide consis-

tent performance over variations of process, supply volt-

age and temperature

TTL compatible driver and control inputs

Designed using Fairchild advanced BiCMOS technology

Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

Power up/down and power off high impedance for live

insertion

Open drain on GTLP to support wired-or connection

Flow through pinout optimizes PCB layout

D-type flip-flop, latch and transparent data paths

A Port source/sink 24mA/ 24mA

B Port sink 50mA

For more information see AN-5026,

Using BGA Packages

REF

Package Description

pin provides external supply reference voltage for

September 2001

Revised July 2002

www.fairchildsemi.com

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gtlp36t612 Summary of contents

Page 1

... GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver General Description The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’ ...

Page 2

Truth Table (Note 3) Inputs Output CEAB OEAB LEAB CLKAB (Note (Note ...

Page 3

... Functional Description The GTLP36T612 is an 36-bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 7) 0. Output Sink Current into A Port Output ...

Page 5

DC Electrical Characteristics Symbol I A Port and V 3.45V (Note 12) Control Pins A or Control Inputs Control Pins i A Port B Port Note 9: All typical values are at V 3.3V, V ...

Page 6

AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature for B Port and for A Port From Symbol (Input PLH t PHL t LEAB PLH ...

Page 7

Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Open PLH PHL PLZ PZL t /t GND PHZ PZH Note A: C includes probes and Jig capacitance. L Voltage Waveform - Propagation ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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