cy7b9514v Cypress Semiconductor Corporation., cy7b9514v Datasheet - Page 6

• Manufacturer Part Number: cy7b9514v
• Description: 3.3v Quad Sonet Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Pin Descriptions
Description
The CY7B9514V Quad Local Area Network ATM Transceiver
can be used in both SONET/SDH and ATM applications to
recover clock and data information from four 155.52-MHz or
51.84-MHz NRZ (Non Return to Zero) or NRZI (Non Return to
Zero Invert on ones) serial data streams. A byte-rate reference
clock is provided by buffering one of the two reference clock
sources.This device also provides a bit-rate Transmit clock, by
multiplying the buffered byte-rate reference clock through the
use of a frequency multiplier PLL and four channels of differ-
ential data buffering for the Transmit side of the system (see
Figure 1 ).
Operating Frequency
The CY7B9514V operates at either of two frequency ranges.
The MODE0 input selects which of the two frequency ranges
the Transmit frequency multiplier PLL and the Receive clock
and data recovery PLLs in all four channels will operate at. The
MODE0 input has three different functional selections. When
MODE0 is connected to V
the device is selected. The device has two reference clock
inputs, REFCLK0 and REFCLK1. REFSEL is used to select
which clock input is used to serve as a reference source for the
Transmit frequency multiplier PLL and the Receive clock and
data recovery PLLs. A 19.44-MHz ±1% source must drive the
selected REFCLK input and the five PLLs will multiply this rate
by 8 to provide output clocks that operate at 155.52 MHz ±1%.
When the MODE0 input is connected to ground (GND), the
lowest operating range of the device is selected. A 6.48-MHz
±1% source must drive the selected REFCLK input and the
five PLLs will multiply this rate by 8 to provide output clocks
that operate at 51.84 MHz ±1%. When the MODE0 input is left
unconnected or forced to approximately V
ters a factory test mode.
Transmit Functions
The transmit section of the CY7B9514V contains a PLL that
takes the selected REFCLK input and multiplies it by 8 (REF-
CLK 8) to produce a PECL (Pseudo ECL) differential output
clock (TCLK±). The transmitter has two operating ranges that
are selectable with the three-level MODE0 pin as explained
above. The CY7B9514V Transmit frequency multiplier PLL al-
lows low-cost byte rate clock sources to be used to time the
upstream serial data transmitter as shown in Figure 1.
Both of the REFCLK inputs are LVTTL-level inputs, allowing
them to be driven by low-cost TTL crystal oscillators, or any
TTL-level clock source.
The four Transmit PECL differential input pairs (TSER±) are
buffered by the CY7B9514V yielding the differential data out-
puts (TOUT±). These outputs can be used to directly drive
transmission media such as Printed Circuit Board (PCB) trac-
es, optical drivers, twisted pair, or coaxial cable.
Name
EAVCC_TCLK Power
DVCC
DVSS
I/O
Power
Gnd
(continued)
CC
, the highest operating range of
Description
Analog Power. Power pin for the TCLK PECL drivers. This pin must be connected to a well
decoupled +3.3V DC supply.
Digital Power. Power pin for the digital logic of the device. This pin must be connected to a well
decoupled 3.3V DC supply.
Digital Ground. Ground pin for the digital logic of the device.
PRELIMINARY
CC
/2, the device en-
6
Receive Functions
The CY7B9514V has four receiver channels. The primary
function of the receivers is to recover clock (RCLK±) and data
(RSER±) from the four different incoming differential PECL
data streams (RIN±) without the need for external buffering.
These built-in line receiver inputs, as well as the TSER± inputs
mentioned above, have a wide common-mode range (1.25V)
and the ability to receive signals with as little as 50 mV differ-
ential voltage. They are compatible with all PECL signals and
any copper media.
The clock recovery function is performed using embedded
PLLs. The recovered clock is not only passed to the RCLK±
outputs, but also used internally to sample the input serial data
stream in order to recover the data pattern. The Receive PLL
uses the selected REFCLK input as a byte-rate reference. This
input is multiplied by 8 (REFCLK 8) and is used to improve
PLL lock time and to provide a center frequency for operation
in the absence of input data stream transitions. The receiver
can recover clock and data in two different frequency ranges
depending on the state of the three-level MODE0 pin as ex-
plained earlier. To insure accurate data and clock recovery,
REFCLK 8 must be within 250 ppm of the transmit bit rate.
The standards, however, specify that the REFCLK 8 frequen-
cy accuracy be within 20 100 ppm.
Carrier Detect (CD) and Link Fault Indicator (LFI)
Functions
The Link Fault Indicator (LFI) outputs are LVTTL-level outputs
that indicate the status of each of the four receivers. These
outputs can be used by an external controller for Loss of Signal
(LOS), Loss of Frame (LOF), or Out of Frame (OOF) indica-
tions. Each LFI output is controlled by the respective Carrier
Detect (CD) input, the internal Transitions Detector, and the
PLL Out of Lock (OOL) circuitry.
Each CD input may be driven by external circuitry that is mon-
itoring the respective incoming data stream. Optical modules
have CD outputs that indicate the presence of light on the op-
tical fiber and some copper based systems use external
threshold detection circuitry to monitor the incoming data
stream. The CD input is a 100K PECL compatible signal that
should be held HIGH when the incoming data stream is valid.
When CD is pulled to a 3.3V PECL LOW (<1.475V Max.), the
LFI output will transition LOW and the Receiver PLL will align
itself with the REFCLK 8 frequency and the recovered data
outputs (RSER) will remain LOW regardless of the signal level
on the Receive data-stream inputs (RIN).
In addition, the CY7B9514V has four built-in transition detec-
tors for each channel that also check the quality of the incom-
ing data stream. The absence of data transitions can be
caused by a broken transmission media, a broken transmitter,
or a problem with the transmit or receive media coupling. The
CY7B9514V will detect a quiet link by counting the number of
CY7B9514V