cy7b9514v Cypress Semiconductor Corporation., cy7b9514v Datasheet - Page 4

• Manufacturer Part Number: cy7b9514v
• Description: 3.3v Quad Sonet Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Pin Descriptions
Name
RIN0±
RIN1±
RIN2±
RIN3±
RSER0±
RSER1±
RSER2±
RSER3±
RCLK0±
RCLK1±
RCLK2±
RCLK3±
CD0
CD1
CD2
CD3
LFI0
LFI1
LFI2
LFI3
TSER0±
TSER1±
TSER2±
TSER3±
TOUT0±
TOUT1±
TOUT2±
TOUT3±
REFCLK0
REFCLK1
TCLK±
LOOP0
LOOP1
LOOP2
LOOP3
I/O
Differential In Receive Input. This line receiver port connects the receive differential serial input data stream to
PECL Out
Differential
PECL Out
Differential
PECL In
Single Ended
LVTTL Out
Differential In Transmit Serial Data. This line receiver port connects the transmit differential serial input data
PECL Out
Differential
LVTTL In
PECL Out
Differential
LVTTL In
Description
the internal Receive PLL. This PLL will recover the embedded clock (RCLK±) and data (RSER±)
information for one of two data rates depending on the state of the MODE pin. These inputs can
receive very low amplitude signals and are compatible with all PECL signaling levels. If the RIN±
inputs are not being used, connect RIN+ to V
Recovered Serial Data. These PECL 100K outputs (+3.3V referenced) are the recovered data
from the input data stream (RIN±). This recovered data is aligned with the recovered clock
(RCLK±) with a set-up and hold window compatible with most data processing devices. All PECL
outputs can be powered down by connecting both outputs to V
nected.
Recovered Clock. These PECL 100K outputs (+3.3V referenced) are the recovered clock from
the input data stream (RIN±). This recovered clock is used to sample the recovered data (RSER±)
and is timing compatible with most data processing devices. If both the RSER± and the RCLK±
are tied to V
Carrier Detect. These inputs control the recovery function of the Receive PLLs and can be driven
by the carrier detect outputs from optical modules or from external transition detection circuitry.
When this input is at a PECL HIGH, the input data stream (RIN±) is recovered normally by the
Receive PLL. When this input is at a PECL LOW, the Receive PLL no longer aligns to RIN±, but
instead aligns with the REFCLK 8 frequency. Also, the Link Fault Indicator (LFI) will transition
LOW, and the recovered data outputs (RSER) will remain LOW regardless of the signal level on
the Receive data-stream inputs (RIN). Each CD input has an internal pull-down resistor.
Link Fault Indicator. These outputs indicate the status of the input data stream (RIN±). It is con-
trolled by three functions; the Carrier Detect (CD) input, the internal Transition Detector, and the
Out of Lock (OOL) detector. The Transition Detector determines if RIN± contains enough transi-
tions to be accurately recovered by the Receive PLL. The Out-of-Lock detector determines if RIN±
is within the frequency range of the Receive PLL. When CD is HIGH and RIN± has sufficient
transitions and is within the frequency range of the Receive PLL, the LFI output will be HIGH. If
CD is at a PECL LOW or RIN± does not contain sufficient transitions or RIN± is outside the
frequency range of the Receive PLL then the LFI output will be LOW (see MODE1).
stream to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can
also be set up to supply the serial input data stream to the Receive PLL. These inputs can receive
very low amplitude signals and are compatible with all PECL signaling levels. If the TSER± inputs
are not being used, connect TSER+ to V
Transmit Output. These PECL 100K outputs (+3.3V referenced) are the buffered version of the
Transmit data stream (TSER±). This Transmit path is used to take weak input signals and rebuffer
them to drive low-impedance copper media or fiber-optic modules. All PECL outputs can be
powered down by connecting both outputs to V
Reference Clocks. One of these inputs is selected by the REFSEL pin as the clock frequency
reference for the clock and data recovery Receive PLL. REFCLK is multiplied internally by eight
and sets the approximate center frequency for the internal Receive PLL to track the incoming bit
stream. This input is also multiplied by eight by the frequency multiplier Transmit PLL to produce
the bit rate Transmit Clock (TCLK±). REFCLK can be connected to a TTL frequency source.
Transmit Clock. These PECL 100K outputs (+3.3V referenced) provide the bit rate frequency
source for external Transmit data processing devices. This output is synthesized by the Transmit
PLL and is derived by multiplying the REFCLK frequency by eight. When this output is turned off,
the entire Transmit PLL is powered down. All PECL outputs can be powered down by connecting
both outputs to V
Loop Back Select. This input is used to select the input data stream source that the Receive PLL
uses for clock and data recovery. When the LOOP input is HIGH, the Receive input data stream
(RIN±) is used for clock and data recovery. When LOOP is LOW, the Transmit input data stream
(TSER±) is used by the Receive PLL for clock and data recovery.
PRELIMINARY
CC
or left unconnected, the entire Receive PLL will be powered down.
CC
or by leaving them both unconnected.
4
CC
and TSER to V
CC
CC
and RIN– to V
or by leaving them both unconnected.
SS
CC
SS
.
.
or by leaving them both uncon-
CY7B9514V