cy7b9514v Cypress Semiconductor Corporation., cy7b9514v Datasheet - Page 5

• Manufacturer Part Number: cy7b9514v
• Description: 3.3v Quad Sonet Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Pin Descriptions
Name
MODE0
MODE1
FC0±
FC1±
FC2±
FC3±
FC_TXP
FC_TXN
REFOUT
REFSEL
PWR_DWN
EAVCC_TX0
EAVCC_TX1
EAVCC_TX2
EAVCC_TX3
AVCC_P1
AVCC_P2
AVCC_P3
AVCC_P4
AVCC_RX0
AVCC_RX1
AVCC_RX2
AVCC_RX3
AVCC_TX
AVSS_P1
AVSS_P2
AVSS_P3
AVSS_P4
AVSS_RX0
AVSS_RX1
AVSS_RX2
AVSS_RX3
AVSS_TX
EAVCC_RX0
EAVCC_RX1
EAVCC_RX2
EAVCC_RX3
I/O
3-Level In
3-Level In
External 1- F
caps
External 1- F
caps
LVTTL Out
LVTTL In
LVTTL In
Power
Power
Gnd
Power
(continued)
Description
Frequency Mode Select. This three-level input selects the frequency range for the clock and data
recovery Receive PLL and the frequency multiplier Transmit PLL. When this input is held HIGH
(V
input is held LOW (V
REFCLK frequency in both operating modes is 1/8 the PLL operating frequency. When the
MODE0 input is left floating or held at V
VCO for use in factory testing.
MODE1 enables the transition detector when it is held HIGH (V
disabled when MODE1 is held LOW (V
the factory test mode is enabled.
These external capacitors are used only to reduce the PLL bandwidth and peaking, when desired.
The PLL lock time will also be increased.
These external capacitors are used only when the slew rate between the two REFCLKs needs to
be reduced.
Reference Output. This output is a buffered version of the selected reference clock. Depending
on the state of the REFSEL pin this output can be a buffered version of REFCLK1 and REFCLK2.
When there is a change of state at the REFSEL, this output will change over from one reference
clock to another reference clock smoothly without glitch, except if TCLK outputs are held HIGH
or left floating.
Reference Select. This pin selects one of the external reference clock (REFCLK 0/1) to be used
as the internal reference clock for the Transmit and Receive PLLs. When this input is at a TTL
HIGH, REFCLK1 is selected. When this input is at a TTL LOW, REFCLK0 is selected.
Power Down. This pin will power down all the PLLs and logic components of the device. When
this pin is held LOW, the Transmit PLL, transition detection logic, and Receive PLLs will power
down. When this pin is held HIGH, the Transmit PLL, transition detection logic, and Receive PLLs
will resume normal operation.
Analog Power. Power pins for the PECL drivers for the TOUT± outputs. These pins must be
connected to a well decoupled 3.3V DC supply.
Analog Power. Power pins for the analog portion of the Receive and Transmit PLLs.
Analog Ground. Ground pins for the analog portion of the Receive and Transmit PLLs.
Analog Power. Power for the PECL RSER and RCLK outputs.These pins must be connected to
a well decoupled +3.3V DC supply.
CC
) the PLLs operate at the SONET (SDH) STS-3 (STM-1) line rate of 155.52 MHz. When this
PRELIMINARY
SS
) the PLLs operate at the SONET STS-1 line rate of 51.84 MHz. The
5
SS
CC
). When the MODE1 input is left floating or held at V
/2, the TSER± inputs substitute for the internal PLL
CC
). The transition detector is
CY7B9514V
CC
/2,