cy7b9514v Cypress Semiconductor Corporation., cy7b9514v Datasheet - Page 11

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cy7b9514v

Manufacturer Part Number
cy7b9514v
Description
3.3v Quad Sonet Transceiver
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Switching Characteristics
Switching Waveforms
f
t
t
t
t
t
t
t
t
t
t
t
Notes:
REF
B
PE
ODC
RF
LOCK
RPWH
RPWL
DV
DH
PD
RL
6.
7.
8.
REFCLK
TOUT
TSER
t
t
The PECL switching threshold is the differential zero crossing (i.e., the place where + and
Parameter
B
LOCK
is calculated as 1/(f
is the time needed for transitioning from lock to REFCLK X8 to lock to data.
REF
Reference Frequency
Bit Time
Receiver Static Phase Error
Output Duty Cycle (TCLK , RCLK )
Output Rise/Fall Time
PLL Lock Time (RIN transition density 25%)
REFCLK Pulse Width HIGH
REFCLK Pulse Width LOW
Data Valid
Data Hold
Propagation Delay (TSER to TOUT)
No Transition Run Length, 25% data field
X8).
t
PD
[6]
t
RPWL
Over the Operating Range
PRELIMINARY
[4]
Description
[4]
t
RPWH
[8]
[4]
11
7B9514V–9
[7]
MODE0=LOW
MODE0=HIGH
MODE0=LOW
MODE0=HIGH
MODE0=LOW
MODE0=HIGH
MODE0=LOW
MODE0=HIGH
signals cross).
19.24
19.50
Min.
6.41
6.50
0.4
45
10
10
3
1
19.64
19.10
Max.
3000
1000
6.55
6.40
200
200
1.2
55
10
75
CY7B9514V
7B9514V–8
MHz
MHz
Unit
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
%
f
B
s
s

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