mpc9894 ETC-unknow, mpc9894 Datasheet - Page 5

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Advanced Clock Drivers Devices
Freescale Semiconductor
Basic Functional Description
generator. The redundancy feature allows automatic
switching from the reference clock source to a secondary
clock source on detection of a failed reference clock. The
MPC9894 will detect and report a missing clock on any of its
four inputs. Based upon the current IDCS mode setting and
the qualifier input pins, the MPC9894 will switch to the next
qualified secondary clock.
are assumed to be the same frequency
related sources. When a clock switch occurs, the phase
alignment to the new clock source will occur over an
extended time period, eliminating runt clock output pulses.
The maximum rate of phase change is specified in the AC
parameter Delta Period per Cycle(
uses a fully integrated PLL to generate clock signals from
redundant clock sources. The PLL multiplies the input
reference clock signal by a variety of values, including 0.25,
0.5, 1, 2, 4 or 8. For a complete list refer to
frequency multiplied clock signal drives four independent
output banks. Each output bank is phase-aligned to the input
reference clock phase, providing virtually zero-delay
capability
generators is performed through either the I
the preset configuration mode. The I
interface to transmit clock and data to and from a series of
configuration and status registers in the MPC9894.
Definitions
IDCS:
clock inputs CLK0, CLK1, CLK2, and CLK3. Upon a failure of
the reference clock signal, the IDCS switches to a qualified
secondary clock signal and the status flags are set.
1. Refer to
2. Using external feedback.
The MPC9894 is a quad-redundancy IDCS clock
The input clock sources, CLK0, CLK1, CLK2, and CLK3,
The configuration of the MPC9894 series of clock
Intelligent Dynamic Clock Switch. The IDCS monitors the
(2)
Table 39
.
for clock frequency specification.
∆
PER/CYC
2
C interface uses a 2 pin
(1)
but non-phase-
2
). The device
Table
C interface or by
OPERATING INFORMATION
9. The
Reference clock signal:
IDCS_MODE[2:0] as the input reference to the PLL.
Primary clock:
primary clock may or may not be the reference clock,
depending on IDCS mode and IDCS status.
Secondary clock:
upon an automatic clock switch.
Tertiary, Quaternary clocks:
in turn, after the current secondary clock. This clock selection
is based upon a round robin rotational sequence
Manual IDCS mode:
IDCS_MODE[0xx].
Automatic IDCS mode:
Selected clock:
signal.
Qualified clock:
the associated CLK_STAT status bit is logic high and no clock
failure is present.
Bit Ordering:
pin and register documentation is NAME[7:0] where bit 7 is
the most significant bit and 0 is the least significant bit.
The input clock signal that is selected by the IDCS or
The input clock signal selected by IDCS_MODE[2:0]. The
The input clock signal which will be selected by the IDCS
The input clock signals that will be selected by the IDCS,
The reference clock input is selected by
The reference clock signal is determined by the IDCS.
The SEL_STAT[1:0] flags indicate the reference clock
The corresponding CLK_VALID[3:0] signal is logic high,
The bit ordering convention used in this document for both
MPC9894
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