mpc9894 ETC-unknow, mpc9894 Datasheet - Page 12

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Output Configuration Register
2 bit-groups with each group selecting the divide ratio for
Mode Configuration Register
read/write register and contains the fields for mode selection
as well as alarm reset.
three least significant Mode Configuration Register bits to the
desired value. The current idcs mode of the MPC9894 may
be obtained by reading this register.
used to individually reset the status flags of register 5. Each
MPC9894
12
Table 12. Output Configuration Register (Register 1 — Read/Write)
Description
Reset default
Preset default
Table 13. PLL Output Divider N (FSEL_A to FSEL_D)
Table 14. Mode Configuration and Alarm Reset Register (Register 2 — Read/Write)
Description
Reset default
Preset default
Table 15. Individual Reset of CLK_STAT[x] Bits
Table 16. MPC9894 IDCS Configuration
1. This is a repeat of
2. For CLK_VALID[3:0] = 1111 and input clock validity.
IDCS_MODE [2:0]
The output configuration register is divided into four,
The mode configuration register, refer to
The mode of the MPC9894 may be changed by writing the
The alarm reset bits, found in bit positions 6 thru 3, may be
ALARM_RST[x]
Bit
Bit
000
001
010
011
100
101
110
111
0
1
not used
Table
n/a
n/a
7
7
No action
The status flag CLK_STAT[x] is cleared by setting of this bit. (bit always reads as zero)
0
0
FSEL_A[1:0]
FSEL_x[1:0]
8.
Description
Automatic
Manual
00
01
10
11
n/a
n/a
6
6
0
0
ALARM_RST[3:0] (Refer to
(1)
Table
Primary clock
n/a
n/a
5
14, is a
5
0
0
CLK0
CLK1
CLK2
CLK3
CLK0
CLK1
CLK2
CLK3
FSEL_B[1:0]
n/a
n/a
4
4
0
0
Secondary clock
Table
output banks A through bank D, refer to
bank, four output divider settings (÷2, ÷4, ÷8, ÷16) are
available, refer to
of these flag bits are associated with the four clock inputs pins
and indicate a failed clock input. Clearing of a clock status
flag is performed by writing a logic 1 to the individual bit (or
bits if more than one flag is to be cleared). Care should be
taken to insure that the idcs mode information is written to the
proper value when resetting the clock status bits. The four
alarm reset bits always read as a logic 0. If a clock input
status flag is cleared and the clock input is still in a failed
state, the status flag will go set within 4 clock cycles after
being cleared.
Description
15)
CLK1
CLK2
CLK3
CLK0
n/a
n/a
n/a
n/a
n/a
n/a
3
3
0
1
FSEL_C[1:0]
(2)
Table
Tertiary clock
IDCS_MODE[2:0] (Refer to
12.
2
2
0
1
0
0
Value
CLK2
CLK3
CLK0
CLK1
n/a
n/a
n/a
n/a
÷16
Advanced Clock Drivers Devices
÷2
÷4
÷8
(2)
Freescale Semiconductor
1
1
1
0
0
1
Table
Quaternary clock
FSEL_D[1:0]
12. For each
CLK3
CLK0
CLK1
CLK2
Table
n/a
n/a
n/a
n/a
0
0
1
0
16)
0
0
(2)