mpc9894 ETC-unknow, mpc9894 Datasheet - Page 17

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Advanced Clock Drivers Devices
Freescale Semiconductor
voltage supply for the device core. The pin SEL_2P5V is
used to logically indicate the core supply voltage. This
selection is done by setting the pin to a logic 1 for 2.5 V or
logic 0 for 3.3 V operation.
3.3 V or 2.5 V and can be individually set for inputs and banks
Power Supply Sequencing and MR Operation
length for
power supply being stable and within V
Refer to
Power Supply Bypassing
differential architecture of the MPC9894 supports low noise
signal operation at high frequencies. In order to maintain its
superior signal quality, all V
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Table 33. Power Supply Configuration
V
V
V
V
V
Supply Voltage
1. V
DD
DDAB
DDCD
DDIC
DDA
The MPC9894 operates from either a 3.3 V or 2.5 V
The input and output supply voltage may be set for either
Figure 5
The MPC9894 is a mixed analog/digital product. The
DDIC
(1)
V
DD
Table 39
(Supply of FB_IN) must be equal to V
MR
Figure 6. V
defines the release time and the minimum pulse
pin. The
Positive power supply for the device core, output status and control inputs. (3.3 V or 2.5 V)
Supply voltage for output banks A and B (QA0 through QB1)
Supply voltage for output banks A and B (QC0 through QD1) and QFB
Supply voltage for differential inputs clock inputs CLK0 to CLK3 and FB_IN
Clean supply for Analog portions of the PLL (This voltage is derived via an RC filter from the V
for actual parameter values. The MPC9894
R
S
CC
MR
TBD
Power Supply Bypass
release time is based upon the
CC
pins should be bypassed by
TBD
TBD
MR
V
DD
DD
specifications.
POWER SUPPLY CONFIGURATION
DDCD
V
V
MPC9894
DD
DDA
(Supply of QFB) to ensure the SPO specification is met.
Figure 5. MR Operation
Description
t
reset_rel
of outputs.
supply pins and what pin or group of pins are associated with
each supply. Note, that for output skew and SPO
specifications to be valid the input, feedback input and output,
and the output bank must all be at the same voltage level.
may be configured after release of reset and the outputs will
be stable for use after lock indication is obtained.
power supply pins. It is recommended that the maximum slew
rate for the V
Clock Outputs
voltage compatible. The outputs are designed to drive a
single 50 Ω impedance load that is properly terminated. The
media pin is used to select between either of two output
termination techniques.
50 Ω parallel terminated (to V
media = 1 the outputs are designed to drive 50 Ω
transmission line terminated with a single 100 differential load
resistor. See
these termination techniques. Note, that the traditional output
pulldown resistors for emitter follower biasing are not
required for the MPC9894. If external feedback is used, the
QFB output must be terminated with the same technique as
selected with the media pin. Once a termination technique is
chosen, that technique must be used for all MPC9894
outputs to guarantee output skew timing.
This provides a simpler termination method and also reduces
overall power consumption of the MPC9894. Unused outputs
may be powered-down via the Output Power-Up and
Feedback Power-Up registers to conserve power. If external
feedback is selected the programming of the PWR_QFB bit
is ignored.
V
The MPC9894 clock outputs are differential LVPECL
Selection of media = 0 sets all of the outputs to drive up to
The recommended termination technique is media = 1.
DD
must ramp up prior to or concurrent with the other
Table 33. Power Supply Configuration
DD
Figure 7
t
reset_pulse
supply not exceed 0.5 V/ms.
and
Figure 8
TT
DD
) transmission lines. With
supply) Derived from V
for diagrams of each of
3.3 V or 2.5 V
3.3 V or 2.5 V
3.3 V or 2.5 V
3.3 V or 2.5 V
Value
lists the
MPC9894
DD
17