mpc9894 ETC-unknow, mpc9894 Datasheet - Page 25

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Advanced Clock Drivers Devices
Freescale Semiconductor
Table 42. Slave Address (Register 0 — Read Only)
Description
Reset default
Preset default
Table 43. Output Configuration Register (Register 1 — Read/Write)
Description
Reset default
Preset default
Table 44. Mode Configuration and Alarm Reset Register (Register 2 — Read/Write)
Description
Reset default
Preset default
Table 45. Device Configuration and Output Clock Enable Register (Register 3 — Read/Write)
Description
Reset default
Preset default
Table 46I. nput and Feedback Divider Configuration Register (Register 4 — Read/Write)
Description
Reset default
Preset default
Table 47. Status Register (Register 5 — Read Only)
Description
Table 48. Output Power-Up Register (Register 6 — Read/Write)
Description
Reset Default
Preset Default
Table 49. Feedback Power-Up Register (Register 7 — Read/Write)
Description
Reset Default
Preset Default
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
INT signal
Inverse of
Reserved
INT
not used
not used
INT_E
7
PWR_QD1
7
0
1
n/a
n/a
n/a
n/a
7
7
7
7
0
0
FSEL_A[1:0]
7
0
1
QUAL_EN
7
Reserved
ADDR_6
6
6
x (TBD)
x (TBD)
0
1
Status of CLK3, CLK2, CLK1 and CLK0 (sticky)
PWR_QD0
n/a
n/a
n/a
n/a
6
6
6
6
0
0
6
0
1
Copy of CLK_STAT[3:0] signal
Slew_Control
ALARM_RST[3:0] (See
6
MPC9894 PROGRAMMING MODEL
5
Reserved
5
0
0
ADD_R5
x (TBD)
x (TBD)
CLK_STAT[3:0]
PWR_QC1
n/a
n/a
n/a
n/a
5
5
5
5
0
0
5
0
1
FSEL_B[1:0]
5
Enable_QFB
4
Reserved
ADDR_4
PWR_QC0
4
x (TBD)
x (TBD)
0
0
n/a
n/a
n/a
n/a
4
4
4
4
0
0
Table
4
0
1
4
15)
ENABLE_QA
3
PWR_QB1
ADDR_3
x (TBD)
x (TBD)
3
0
1
n/a
n/a
3
3
3
3
0
1
0
0
3
0
1
FSEL_C[1:0]
3
Inverse of LOCK
ENABLE_QB
ADDR[2] pin
LOCK
signal
PWR_QB01
read from
ADDR_2
2
2
0
1
Input_FB_Div[3:0]
2
2
2
IDCS_MODE[2:0] (See
2
0
0
0
1
0
0
2
0
1
2
ENABLE_QC
ADR[1] pin
read from
Copy of SEL_STAT[1:0]
PWR_QA1
ADDR_1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
SEL_STAT[1:0]
1
1
0
1
FSEL_D[1:0]
signal
Table
ENABLE_QD
ADDR[0] pin
PWR_QFB
PWR_QA0
read from
ADDR_0
MPC9894
16)
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
1
25