mpc9894 ETC-unknow, mpc9894 Datasheet - Page 14

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Input and Feedback Divider Configuration Register
used to select the input divider value and the feedback divider
values. The four bits for Input_FB_Div allow 16 combinations
of input and feedback divider ratios. Some input and output
Device Status Register
SEL_STAT[1:0], LOCK and CLK_STAT[3:0] pins. In addition,
bit 7 is an INT flag bit, which is used to indicate a setting of a
bit in the CLK_STAT[3:0], a clearing of the LOCK bit and a
change in the value of the SEL_STAT[1:0] bits.
MPC9894
14
Table 22. Input and Feedback Divider Configuration Register (Register 4 — Read/Write)
Description
Reset default
Preset default
Table 23. Input_FB_Div[3:0]
Table 24. Status Register (Register 5 — Read Only)
Description INT
The Input and Feedback Divider Configuration Register is
The Device Status Register contains a copy of the status
Bit
Bit
Input_FB_Div[3:0]
Inverse of
signal
Reserved
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
7
n/a
n/a
7
INT
CLK_STAT[3:0]
Status of CLK3, CLK2, CLK1 and CLK0 (sticky)
Copy of CLK_STAT[3:0] signal
Reserved
6
n/a
n/a
6
Reserved
5
n/a
n/a
5
Input Divider (P)
Reserved
4
n/a
n/a
1
1
2
1
2
2
3
4
4
4
6
4
frequency ranges may overlap allowing a choice of PLL
closed loop bandwidths. This selection may be useful when
PLL devices are cascaded.
manually reset through the Mode Configuration Register.
interrupt pin only if interrupts are enabled. Enabling interrupts
is done by the setting of the INT_E bit which is located in the
Device Configuration Register. Reading of the Status
Register clears the INT flag.
The CLK_STAT[3:0] bits are sticky and remain set until
The setting of the register INT bit is reflected on the
3
3
0
0
reserved
reserved
reserved
reserved
reserved
LOCK
Inverse of
signal
2
Input_FB_Div[3:0]
LOCK
2
0
0
Advanced Clock Drivers Devices
Feedback Divider (M)
SEL_STAT[1:0]
Copy of SEL_STAT[1:0] signal
Freescale Semiconductor
16
12
12
16
12
16
12
12
1
8
8
8
1
0
1
0
0
0
1