ics9lprs365 Integrated Device Technology, ics9lprs365 Datasheet - Page 20

• Manufacturer Part Number: ics9lprs365
• Description: 64-pin Ck505 W/fully Integrated Voltage Regulator + Integrated Series Resistor
• Manufacturer: Integrated Device Technology

1218—09/01/10
Note 1 : When 27_Select pin = 0, B1b7 PWD = 1, , when 27_Select pin = 1, PWD = 0
Byte 0 FS Readback and PLL Selection Register
Byte 1 DOT96 Select and PLL3 Quick Config Register
Byte 2 Output Enable Register
Byte 3 Output Enable Register
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
13/14
17/18
Pin
Pin
Pin
Pin
-
-
-
-
-
-
-
-
PLL1_SSC_SEL
SRC_Main_SEL
SRC8/ITP_OE
PD_Restore
SATA_SEL
SRC0_SEL
SRC11_OE
SRC10_OE
PCIF5_OE
PLL3_CF3
PLL3_CF2
PLL3_CF1
PLL3_CF0
SRC9_OE
SRC7_OE
SRC6_OE
SRC4_OE
iAMT_EN
Reserved
Reserved
PCI_SEL
PCI4_OE
PCI3_OE
PCI2_OE
PCI1_OE
PCI0_OE
Reserved
REF_OE
USB_OE
Name
Name
Name
Name
FSLC
FSLB
FSLA
state else clear all config as if cold power on and go
Set via SMBus or dynamically by CK505 if detects
If config saved, on deassert return to last known
Output enable for REF, if disabled output is tri-
CPU Freq. Sel. Bit (Least Significant)
CPU Freq. Sel. Bit (Most Significant)
Select 0.5% down or center SSC
Output enable for SRC8 or ITP
Select source for SATA clock
Select source for SRC Main
Output enable for SRC11
Output enable for SRC10
PLL3 Quick Config Bit 3
PLL3 Quick Config Bit 2
PLL3 Quick Config Bit 1
PLL3 Quick Config Bit 0
Output enable for SRC9
Output enable for SRC7
Output enable for SRC6
Output enable for SRC4
Select SRC0 or DOT96
Output enable for PCI5
Output enable for PCI4
Output enable for PCI3
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
Output enable for USB
to latches open state
CPU Freq. Sel. Bit
Description
dynamic M1
Description
Description
Description
Reserved
PCI_SEL
Reserved
stated
20
(Sticky
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit)
R
R
R
R
SRC Main = PLL1 SRC Main = PLL3
Configuration Not
See Table 1 : CPU Frequency Select
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
See Table 2: pin17, 18 Configuration
PCI from PLL1
Legacy Mode
Down spread
Only applies if Byte 0, bit 2 = 0.
SRC_Main
SATA =
Saved
SRC0
0
0
0
0
Table
ICS9LPRS365
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
PCI from PLL3
iAMT Enabled
SATA = PLL2
Center spread
Configuration
DOT96
Saved
Datasheet
1
1
1
1
Default
Default
Default
Default
Note 1
Latch
Latch
Latch
1
0
0
0
0
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1