ics9lprs365 Integrated Device Technology, ics9lprs365 Datasheet
ics9lprs365
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ics9lprs365 Summary of contents
Page 1
... SRC PCI REF MHz MHz MHz MHz 100.00 33.33 14.318 Reserved and V specifications in IL_FS IH_FS and V IL_FS IH_FS ICS9LPRS365 Datasheet Pin Configuration PCI0/CR# SCLK VDDPCI 2 63 SDATA PCI1/CR# REF0/FSLC/TEST_SEL PCI2/TME 4 61 VDDREF PCI3 PCI4/27_Select PCI_F5/ITP_EN 7 58 GNDREF GNDPCI 8 ...
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... True clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0, OUT 0=DOT96 Complement clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0, OUT 0=DOT96 PWR Ground pin for the DOT96 clocks. PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. 2 ICS9LPRS365 Datasheet DESCRIPTION ...
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... SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be I/O set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit SRC11# enabled (default) 1= CR#_G controls SRC9 3 ICS9LPRS365 Datasheet DESCRIPTION ...
Page 4
... Pin 7 latched input Value 0 = SRC8 ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: OUT Pin 7 latched input Value 0 = SRC8 1 = ITP N/A No Connect 4 ICS9LPRS365 Datasheet DESCRIPTION ...
Page 5
... CPU frequency selection. Refer to I/O input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. I/O Data pin for SMBus circuitry, 5V tolerant. IN Clock pin of SMBus circuitry, 5V tolerant. 5 ICS9LPRS365 Datasheet DESCRIPTION ...
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... MLF 0 DOT96, LCD_SS SRC0, 27MHz Non SS & SS Byte1 bit7 = 1 Byte1 bit7 ICS9LPRS365 Datasheet SRCT6 47 SRCC6 46 VDDSRC 45 PCI_STOP# 44 CPU_STOP# 43 VDDSRC_IO 42 SRCC10 41 SRCT10 40 SRCT11/CR#_H 39 SRCC11/CR#_G 38 SRCC9 37 SRCT9 36 GNDSRC 35 SRCC4 34 SRCT4 ...
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... Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 53 and I/O 54 are an ITP or SRC pair. 0 =SRC8/SRC8 ITP/ITP# PWR Ground for PCI clocks. PWR Power supply for USB clock, nominal 3.3V. 7 ICS9LPRS365 Datasheet ...
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... SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC I/O pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair 8 ICS9LPRS365 Datasheet ...
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... Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted IN in from the ICH to set the FSC, FSB, FSA values PWR VDD pin for SRC Pre-drivers, 3.3V nominal OUT Complement clock of low power differential SRC clock pair. OUT True clock of low power differential SRC clock pair. 9 ICS9LPRS365 Datasheet ...
Page 10
... Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for IN Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. 10 ICS9LPRS365 Datasheet ...
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... General Description ICS9LPRS365 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPRS365 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. ...
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... PLL3 Single-ended Out 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 0.8V IO supply, Power Down Mode 3.3V supply, iAMT Mode 0.8V IO supply, iAMTMode Logic Inputs IN Output pin capacitance X1 & X2 pins Triangular Modulation 12 ICS9LPRS365 Datasheet MIN MAX UNITS 4.6 V 3.8 V 4.6 V GND - 0.5 V ° -65 150 C 115 ° ...
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... Single-ended Measurement XABSVAR D Differential Measurement CYC Differential Measurement C2C Differential Measurement C2C Differential Measurement C2C Differential Measurement SKEW10 Differential Measurement SKEW20 Differential Measurement SKEW =22Ω (unless specified otherwise ICS9LPRS365 Datasheet MIN MAX UNITS Notes 2 1000 ns 1 300 ...
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... Measured from 2.0 to 0.8 V FLR 1 1.5 V skew 1.5 V delay 1.5 V jcyc-cyc T 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 1.0ns 14 ICS9LPRS365 Datasheet NOTES MIN MAX UNITS 1,2 -300 300 ppm 30.00900 ns 29.99100 30.15980 ns 29.49100 30.65980 ns 2.4 V 0.4 V - ...
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... OH V @MAX = 3.135 MIN = 1. MAX = 0 Measured from 0.8 to 2.0 V SLR t Measured from 2.0 to 0.8 V FLR 1 1.5 V jcyc-cyc T 15 ICS9LPRS365 Datasheet NOTES MIN MAX UNITS -100 100 ppm 1,2 20.83125 20.83542 ns 2 20.48130 21.18540 -23 ...
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... Number of Loads Actually Driven. Match Point for N & P Voltage / Current (mA) 1 Load Loads Rs= 3 Loads Ω [39 Ω ] (17 Ω Ω [43 Ω ] (14 Ω Ω [43 Ω ] (11.6 Ω ICS9LPRS365 Datasheet MIN MAX UNITS Notes -300 300 ppm 69.8203 69.8622 ns 69.8203 70.86224 ns 2 ...
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... N/A N/A 0 N/A N/A 1 N/A N/A 0 N/A N/A 1 N/A N/A 17 ICS9LPRS365 Datasheet U DOT SB MHz MHz 48.00 96.00 Spread Comment % PLL 3 disabled 0.5% Down Spread SRCCLK1 from SRC_MAIN 0.5% Down Spread Only SRCCLK1 from PLL3 1% Down Spread Only SRCCLK1 from PLL3 1.5% Down Spread Only SRCCLK1 from PLL3 2% Down Spread Only SRCCLK1 from PLL3 2 ...
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... Register OE Free-run Stoppable X Enable Running Running X Enable Low Low X Enable Running Low X Low Low Disable Low Low 18 ICS9LPRS365 Datasheet CPU(0,2) CPU(0,2)# Running Running Low/20K Low High Low Low/20K Low Low/20K Low SRC/LCD SRC#/LCD# DOT DOT# PCI Stoppable/CR Selected Running Running ...
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... General SMBus serial interface information for the ICS9LPRS365 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the beginning byte location = N • ICS clock will acknowledge • ...
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... Description Output enable for SRC11 Output enable for SRC10 Output enable for SRC9 Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Reserved Output enable for SRC4 20 ICS9LPRS365 Datasheet Type See Table 1 : CPU Frequency Select R Table R ...
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... Enable CR#_F (clk req) -> SRC8 Enable CR#_G (clk req) -> SRC9 Enable CR#_H (clk req) -> SRC10 Reserved Reserved If set, LCD_SS stops with PCI_STOP# If set, SRCs stop with PCI_STOP# Description Revision ID Vendor ID ICS is 0001, binary 21 ICS9LPRS365 Datasheet Type Output Disabled Output Enabled RW Output Disabled Output Enabled RW ...
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... Output enable for SE2 Description Allows control of PCIF5 with assertion of PCI_STOP# Sets the REF output drive strength IO Output Voltage Select Description Readback of 27_Select latch Reserved Reserved M1 mode clk enable Reserved Description Reserved Reserved 22 ICS9LPRS365 Datasheet Type See Device ID Table ...
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... SSP10 1 SSP9 0 SSP8 1218—09/01/10 Description Read Back byte count register, max bytes = 32 Description N Divider 8 N Divider 9 latch-in or Byte 0 Rom table. Description Byte 0 Rom table. Description values. Description Reserved values. 23 ICS9LPRS365 Datasheet Type Type ...
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... M/N Enable *These bits are disabled if TME is latched to 1 1218—09/01/10 Description N Divider 8 N Divider 9 latch-in or Byte 0 Rom table. Description Byte 0 Rom table. Description values. Description Reserved values. Description CPU PLL M/N Enable SRC/PCI PLL M/N Enable 24 ICS9LPRS365 Datasheet Type ...
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... If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z) 1218—09/01/10 ICS9LPRS365 HW FSLC/ FSLB/ TEST TEST_SEL TEST_MODE ENTRY BIT ...
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... α aaa VARIATIONS SEATING SEATING PLANE PLANE Reference Doc.: JEDEC Publication 95, MO-153 aaa C 10-0039 26 ICS9LPRS365 Datasheet 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN -- 1.20 -- 0.05 0.15 .002 0.80 1.05 .032 0.17 0.27 .007 0.09 0.20 ...
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... SYMBOL MIN. MAX. A 0.8 1 0.05 A3 0.25 Reference b 0.18 0.3 e 0.50 BASIC 9.00 x 9.00 7.00 7.25 7.00 7.25 0.30 0.50 Marking Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel 27 ICS9LPRS365 Datasheet OPTION 2 DIMENSIONS (mm) SYMBOL MIN. MAX. A 0.8 1 0.05 A3 0.25 Reference b 0.18 0.3 e 0.50 BASIC BASIC 9.00 x 9.00 D2 MIN. / MAX. 6.00 6.25 E2 MIN. / MAX. 6.00 6.25 L MIN. / MAX. 0.30 0.50 Package ...
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... Update Table2, SMBus Byte1 table, added 27_Select tables for TSSOP 0.97 1/28/2009 and MLF 0.98 4/1/2009 Update SEL27 and ITP_EN pin descriptions. 0.99 9/9/2009 Added updated ordering information table and marking diagrams. 9/1/2010 A Updated PLL3 Quick Configuration table 1218—09/01/10 ICS9LPRS365 28 Datasheet Page # - 12 2-5, 7-10, 22-23 23 4,9, 19 Various ...