ics8624 Integrated Device Technology, ics8624 Datasheet - Page 6

• Manufacturer Part Number: ics8624
• Description: Differential-input Hstl-output 1 5 700-mhz Clock Zero-delay Buffer
• Manufacturer: Integrated Device Technology

3.3V C
8624BY
O
P
O
nQ0:nQ4
nQx
nQy
HASE
UTPUT
UTPUT
nQ
nFB_IN
Q0:Q4
Qy
nCLK0,
3.3V±5% or 10%
FB_IN
nCLK1
V
V
HSTL
CLK0,
(where t (Ø) is any random sample, and t (Ø)
of the sampled cycles measured on controlled edges)
CLK1
DD
DDA
,
J
ORE
V
GND
1.8V±0.2V
0V
ITTER AND
DDO
S
P
KEW
ULSE
/1.8V O
➤
t jit(Ø) = t (Ø) — t (Ø)
t (Ø)
V
Integrated
Circuit
Systems, Inc.
W
DDO
➤
t (Ø)
t sk(o)
2
Pulse Width
IDTH
S
UTPUT
TATIC
mean
/P
ERIOD
= Static Phase Offset
L
P
P
OAD
HASE
t
ARAMETER
PERIOD
mean
AC T
O
V
FFSET
DDO
= Phase Jitter
2
EST
C
mean
www.icst.com/products/hiperclocks.html
nQx
Qx
IRCUIT
is the average
SCOPE
M
EASUREMENT
V
DDO
2
V
V
V
V
OH
OL
OH
OL
D
6
nQ0:nQ4
C
O
P
D
IFFERENTIAL
Clock
Outputs
nCLK0,
nCLK0,
nCLK1
nCLK1
CLK0,
Q0:Q4
ROPAGATION
YCLE
UTPUT
IFFERENTIAL
CLK0,
CLK1
CLK1
nQx
GND
Qx
V
DD
-
TO
R
-C
V
ISE
20%
➤
I
PP
YCLE
NFORMATION
/F
I
D
NPUT
ALL
ELAY
-
t
TO
J
jit(cc) =
t
cycle n
ITTER
T
t
PD
L
80%
-HSTL Z
IME
t
EVEL
R
1000 Cycles
t
cycle n –
Cross Points
➤
➤
ERO
L
t
OW
cycle n+1
t
cycle n+1
D
S
80%
ICS8624
t
ELAY
KEW
F
REV. C JUNE 15, 2004
, 1-
B
➤
20%
UFFER
V
TO
CMR
V
-5
OD