ics8624 Integrated Device Technology, ics8624 Datasheet - Page 10

• Manufacturer Part Number: ics8624
• Description: Differential-input Hstl-output 1 5 700-mhz Clock Zero-delay Buffer
• Manufacturer: Integrated Device Technology

The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
C
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
8624BY
OWER AND
LOCK
T
RACES AND
U1
Pin 1
G
ROUNDING
Integrated
Circuit
Systems, Inc.
DDA
C1
pin as possible.
C6
T
ERMINATION
R7
C16
C11
F
IGURE
www.icst.com/products/hiperclocks.html
4B. PCB B
OARD
10
C7
C2
D
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
IFFERENTIAL
L
AYOUT
• The differential 50Ω output traces should have same
• Avoid sharp angles on the clock trace. Sharp angle
• Keep the clock traces on the same layer. Whenever pos-
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal traces are routed between the
• The matching termination resistors should be located as
length.
turns cause the characteristic impedance to change on
the transmission lines.
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
clock trace pair.
close to the receiver input pins as possible.
C5
C4
F
OR
ICS8624
-
TO
-HSTL Z
ERO
L
OW
D
S
ICS8624
ELAY
KEW
REV. C JUNE 15, 2004
GND
50 Ohm
Traces
VDDO
VDD
VDDA
VIA
, 1-
B
UFFER
TO
-5