mt46v128m8p-6t Micron Semiconductor Products, mt46v128m8p-6t Datasheet - Page 81

• Manufacturer Part Number: mt46v128m8p-6t
• Description: 1gb Ddr Sdram Component
• Manufacturer: Micron Semiconductor Products

Power-down (CKE Not Active)
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command, until completion of the
access. Thus a clock suspend is not supported. For READs, an access completion is
defined when the read postamble is satisfied; for WRITEs, when the write recovery time
(
Power-down, as shown in Figure 53 on page 82, is entered when CKE is registered LOW
and all criteria in Table 27 on page 38 are met. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when a
row is active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CK, CK#, and CKE. For
maximum power savings, the DLL is frozen during precharge power-down mode. Exiting
power-down requires the device to be at the same voltage and frequency as when it
entered power-down. However, power-down duration is limited by the refresh require-
ments of the device (
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-
down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.
t
WR) is satisfied.
t
REFC).
81
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Operations