mt48lc16m16a2 Micron Semiconductor Products, mt48lc16m16a2 Datasheet - Page 28

• Manufacturer Part Number: mt48lc16m16a2
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

CLOCK SUSPEND
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the in-
put pins at the time of a suspended internal clock edge
is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Fig-
ures 22 and 23.)
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
COMMAND
INTERNAL
ADDRESS
NOTE: For this example, burst length = 4 or greater, and DM
The clock suspend mode occurs when a column ac-
For each positive clock edge on which CKE is
CLOCK
Clock Suspend During WRITE Burst
CKE
CLK
D
IN
is LOW.
NOP
T0
WRITE
BANK,
COL n
D
T1
n
IN
Figure 22
T2
T3
NOP
n + 1
T4
D
IN
T5
n + 2
NOP
D
IN
28
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the pro-
grammed burst length and sequence, just as in the
normal mode of operation (M9 = 0).
COMMAND
INTERNAL
ADDRESS
CLOCK
The burst read/single write mode is entered by pro-
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
Clock Suspend During READ Burst
CKE
CLK
DQ
Clock suspend mode is exited by registering CKE
DQM is LOW.
T0
BANK,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COL n
READ
T1
NOP
Figure 23
256Mb: x4, x8, x16
T2
NOP
D
OUT
n
T3
n + 1
D
OUT
T4
NOP
©2002, Micron Technology, Inc.
T5
SDRAM
NOP
n + 2
D
OUT
DON’T CARE
T6
NOP
D
n + 3
OUT