sg5842jasz-f116 Fairchild Semiconductor, sg5842jasz-f116 Datasheet - Page 9

• Manufacturer Part Number: sg5842jasz-f116
• Description: Sg5842 ? Highly Integrated Green-mode Pwm Controller
• Manufacturer: Fairchild Semiconductor

Highly Integrated Green-Mode PWM Controller
OPERATION DESCRIPTION
Start-up Current
The typical start-up current is only 14µA, which allows a
high-resistance, low-wattage start-up resistor to be used to
minimize power loss. A 1.5MΩ, 0.25W, start-up resistor
and a 10µF/25V V
AC/DC adapter with a universal input range.
Operating Current
The required operating current has been reduced to 4mA.
This results in higher efficiency and reduces the V
hold-up capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to continuously decrease the PWM frequency
under light-load conditions. To avoid acoustic noise
problems, the minimum PWM frequency is set above
22KHz. This green-mode function dramatically reduces
power consumption under light-load and zero-load
conditions. Power supplies using a SG5842A/JA
controller can meet even the most restrictive international
regulations regarding standby power consumption.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the SG5842A/JA
controller. This current is used to determine the center
PWM frequency. Increasing the resistance reduces PWM
frequency. Using a 26KΩ resistor, R
corresponding 65KHz PWM frequency. The relationship
between R
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
SG5842JA also integrates frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency hopping function helps reduce EMI emission
of a power supply with minimum line filters.
© System General Corp.
Version 1.4.2 (IAO33.0026.B6)
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PWM
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hold-up capacitor are sufficient for an
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- 9 -
Leading-Edge Blanking
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch off
the gate drive.
Under-Voltage Lockout (UVLO)
The turn-on/turn-off thresholds are fixed internally at
16.5V/10.5V. To enable a SG5842A/JA controller during
start-up, the hold-up capacitor must first be charged to
16.5V through the start-up resistor.
The hold-up capacitor continues to supply V
energy can be delivered from the auxiliary winding of the
main transformer. V
this start-up process. This UVLO hysteresis window
ensures that the hold-up capacitor can adequately supply
V
Gate Output / Soft Driving
The SG5842A/JA BiCMOS output stage is a fast totem
pole gate driver. Cross-conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect the power MOSFET
transistors from any harmful over-voltage gate signals. A
soft driving waveform is implemented to minimize EMI.
Slope Compensation
The sensed voltage across the current sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. The built-in slope compensation
function improves power supply stability and prevents
peak-current-mode control from causing sub-harmonic
oscillations.
SG5842A/JA controller produces a positively sloped,
synchronized ramp signal.
DD
during start-up.
www.sg.com.tw • www.fairchildsemi.com
Within
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must not drop below 10.5V during
every
Product Specification
switching
October 30, 2007
SG5842A/JA
cycle,
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before
the