st52f513 STMicroelectronics, st52f513 Datasheet - Page 88

• Manufacturer Part Number: st52f513
• Description: 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

ST52510xx ST52513xx
14 I
14.1 Introduction
The I
between the microcontroller and the serial I
providing both multimaster and slave functions and
controls all I
arbitration and timing. The
supports fast I
14.2 Main Features
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I
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I
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Figure 14.1 I
88/136
2
2
C Master Features:
C Slave Features:
Parallel-bus/I
Multi-master capability
7-bit/10-bit Addressing
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
Acknowledge Failure Flag
Clock generation
I
Arbitration Lost Flag
End of byte transmission flag
Transmitter/Receiver Flag
Start bit detection flag
Start and Stop generation
Stop bit detection
I
Detection of misplaced start or stop condition
Programmable I
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
2
2
C bus busy flag
C bus busy flag
2
C BUS INTERFACE (I
2
C Bus Interface serves as an interface
SCL
SDA
2
C bus-specific sequencing, protocol,
2
2
CONDITION
C mode (400kHz).
C BUS Protocol
2
C protocol converter
START
2
C Address detection
2
C)
MSB
1
I
2
Bus Interface
2
2
C bus,
14.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
via software. The interface is connected to the I
bus by a data pin (SDA) and by a clock pin (SCL).
The interface can be connected both with a
standard I
selection is made via software.
14.3.1 Mode Selection.
The interface can operate in the following four
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP
capability.
14.3.2 Communication Flow.
In Master mode, Communication Flow initiates
data transfer and generates the clock signal. A
serial data transfer always begins with a start
condition and ends with a stop condition. Both start
and stop conditions are generated in master mode
by software.
In Slave mode the interface is capable of
recognizing its own address (7 or 10-bit) and the
General Call address. The General Call address
detection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
(MSB first). The first byte following the start
condition is the address (one in 7-bit mode, two in
10-bit mode), which is always transmitted in
Master mode.A 9th clock pulse follows the 8 clock
cycles of a byte transfer, during which the receiver
must send an acknowledge bit to the transmitter.
Refer to
8
Figure
generation,
2
C bus and a Fast I
14.1.
ACK
9
CONDITION
providing
STOP
2
C bus. This
Multi-Master
2
C