st52f513 STMicroelectronics, st52f513 Datasheet - Page 50

• Manufacturer Part Number: st52f513
• Description: 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

ST52510xx ST52513xx
6.5 Register Description
The following section describes the Register which
are used to configure the Clock, Reset and PLVD.
6.5.1 Configuration Register.
CPU Clock Prescaler (CPU_CLK)
Configuration Register 46 (02Eh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5-0: CPUCK5-0 CPU Clock Prescaler bits
6.5.2 Option Bytes.
Clock Mode (OSC_CR)
Option Byte 0 (00h)
50/136
7
7
-
-
CPUCK5-0
The CPU Clock frequency is divided by a
factor described in the following table
000000
000001
000010
000100
001000
010000
100000
-
-
others
CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0
-
-
-
f
f
f
f
f
f
f
CPU
CPU
CPU
CPU
CPU Clock
CPU
CPU
CPU
f
CPU
=f
=f
=f
=f
-
=f
=f
=f
=f
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
/16
/32
/64
/64
/2
/4
/8
-
CKMOD
0
0
Bit 7-2: Not Used
Bit 1: Must be set to 0
Bit 0: CKMOD Clock Mode
External Clock Parameters (CLK_SET)
Option Byte 1 (01h)
Bit 7-3: Not Used
Bit 2-0: CKPAR2-0 Oscillator Gains
Warning: If an External Clock is used instead of a
quartz or ceramic resonator, it is recommended
that no gain be enabled (CKPAR2-0=000) in order
lo lower the current consumption.
CKPAR2-0
7
-
000
001
010
100
101
011
110
111
0: Internal Oscillator
1: External Clock or quartz
These three bits enable/disable the loop
gains when a external clock or quartz are
used for generating the clock. The
following table describes the possible
configuration options.
the recommended values for the most
common frequencies used, time to start the
oscillations and the settling time to have a
duty cycle of 40%-60% (at steady state it is
50%).
-
-
No Gains (External Clock Mode)
-
Enabled Gain Stages
1 gain stage enabled
3 gain stage enabled
6 gain stage enabled
8 gain stage enabled
not allowed
not allowed
not allowed
-
Table 6.1
CKPAR2 CKPAR1 CKPAR0
illustrates
0