st52f513 STMicroelectronics, st52f513 Datasheet - Page 23

• Manufacturer Part Number: st52f513
• Description: 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

3 ADDRESSING SPACES
ST52F510/F513 has six separate addressing
spaces:
■
■
■
■
■
■
Note: stack is in the same address space of
Program memory.
Each space is addressed by a load type instruction
that indicates the source and the destination space
in the mnemonic code (see
3.1 Memory Interface
The read/write operation in the space addresses
are managed by the Memory Interface, which can
recognize the type of memory addressed and set
the appropriate access time and mode.
In addition, the Memory Interface manages the In
Application Programming (IAP) functions in Flash
devices like writing cycle and memory write
protection.
Figure 3.1 Addressing Spaces
Register File
Program/Data Memory and Stacks
Input Registers
Output Registers
Configuration Registers
Fuzzy Registers
PROGRAM/DATA MEMORY
NON VOLATILE MEMORY
LDPE
RAM BANKS
AND STACKS
LDCE
LDER
Figure
LDRE
3.1).
INPUT REGISTERS
REGISTER FILE
STFive CORE
LDFR
LDRI
LDCNF
GETPG
3.2 Register File
The Register File consists of 256 general purpose
8-bit RAM locations called “registers” in order to
recall the functionality.
The Register File exchanges data with all the other
addressing spaces and is used by the ALU to
perform all the arithmetic and logic instructions.
These instructions have any Register File address
as operands.
Data can be moved from one location to another by
using the LDRR instruction; see further ahead for
information on the instruction used to move data
between
addressing spaces.
3.3 Program/Data Memory
The Program/Data Memory consists of both non-
volatile memory (Flash, EEPROM) and RAM
memory benches.
Non-volatile memory (NVM) is mainly used to store
the user program and can also be used to store
permanent data (constant, look-up tables).
Each RAM bench consists of 256 locations used to
store run-time user data. At least one bench is
present in the devices. RAM benches are also
used to implement both System and User Stacks.
NVM & RAM locations can be accessed by means
of the LDER and LDRE instructions.
PROCESSOR
REGISTERS
DECISION
PROGRAM
COUNTER
DPU
ALU
CU
PGSETR
the
LDPR
LDCR
Register
CONFIGURATION
ST52510xx ST52513xx
REGISTERS
ON CHIP PERIPHERALS
REGISTERS
OUTPUT
File
and
PERIPHERAL
PERIPHERAL
PERIPHERAL
BLOCK
BLOCK
BLOCK
the
23/136
other