st52f513 STMicroelectronics, st52f513 Datasheet - Page 21

• Manufacturer Part Number: st52f513
• Description: 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

Each interrupt level has its own set of flags, which
is saved in the Flag Stack during interrupt
servicing. These flags are restored from the Flag
Stack automatically when a RETI instruction is
executed.
If the ICU was in normal mode before an interrupt,
after the RETI instruction is executed, the normal
flags are restored.
Note: A subroutine CALL is a normal mode
execution. For this reason a RET instruction,
consequent to a CALL instruction, doesn’t affect
the normal mode set of flags.
Flags are not cleared during context switching and
remain in the state they were in at the exit of the
last interrupt routine switching.
The Carry flag is set when an overflow occurs
during arithmetic operations, otherwise it
cleared. The Sign flag is set when an underflow
occurs during arithmetic operations, otherwise it is
cleared.
The flags, related to the current context, can be
checked by reading the FLAGS Input Register 38
(026h).
Figure 2.3 Multiplication
REG. j
LSB
0FDh
0FEh
000h
001h
0FFh
002h
j-1
j
j+1
i
RAM
X
16 Bit
MSB
REG. i
is
2.2 Arithmetic Logic Unit
The 8-bit Arithmetic Logic Unit (ALU) performs
arithmetic calculations and logic instructions such
as: sum, subtraction, bitwise AND, OR, XOR, bit
set and reset, bit test and branch, right/left shift and
rotate (see
details).
In addition, the ALU of ST52F510/F513 can
perform multiplication (MULT) and division (DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values); the
division instruction addresses the MSB of the
dividend (the LSB is stored in the next address):
the result and remainder are stored in these source
addresses (see
In order to manage signed type values, the ALU
also performs addition and subtraction with offset
(ADDO
respectively subtract and add 128 to the overall
result, in order to manage values logically in the
range between -128,127.
Figure 2.4 Division
and
Chapter 9
REG. j
Figure 2.3
SUBO).
REMAINDER
001h
0FDh
0FEh
0FFh
000h
002h
i-1
i+1
j-1
j
j+1
ST52510xx ST52513xx
i
REG. j+1
Instruction Set for further
and
RAM
These
Figure
:
QUOTIENT
REG. i
2.4).
instructions
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