cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 95

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

Table 13-25. SRAM Write Cycle Latency from Second Cycle of Learn Instruction
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
Document #: 38-02042 Rev. *E
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
• Cycle 1B: The host ASIC continues to drive CMDV to 1, CMD[1:0] to 11, and CMD[5:2] with the comparand pair index. CMD[6]
• Cycle 2: The host ASIC drives CMDV to 0.
of the comparand register pair that will be written to the data array in the 136-bit-configured table. For a Learn in a 68-bit-con-
figured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven
on SADR[21:19] in the SRAM Write cycle.
must be set to 0 if the Learn is being performed on a 68-bit-configured table, and to 1 if the Learn is being performed on a
136-bit-configured table.
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
SADR[21:0]
CMD[1:0]
CMD[8:2]
CLK2X
PHS_L
CMDV
WE_L
OE_L
CE_L
SSV
SSF
TLSZ = 01, LRAM = 1, LDEV = 1.
DQ
Figure 13-71. Learn Timing Diagram on Device Number 7 (TLSZ = 01)
z
z
1
1
0
0
0
Comp1
cycle
Learn1
1A 1B
1
X
cycle
2
X
X
X
X
cycle
Comp2
Learn2
3
X
cycle
4
X
X
X
X
cycle
5
z
cycle
Latency in CLK Cycles
1
6
cycle
z
7
z
z
cycle
4
5
6
8
1
1
cycle
z
9
z
z
cycle
10
z
1
1
0
CYNSE70032
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