cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 22

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

The following is the Write operation sequence, and Table 12-7 shows the Write address format for the data array, the mask array,
or the single-Write SRAM. Table 12-8 shows the Write address format for the internal registers.
At the termination of cycle 3, another operation can begin.
described above (see Subsection 15.2, “SRAM PIO Access” on page 99).
Figure 12-4 shows the timing diagram of a burst Write operation of the data or mask array.
Table 12-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write)
Table 12-8. Write Address Format for Internal Registers
Document #: 38-02042 Rev. *E
Reserved 0: Direct
Reserved 0: Direct
Reserved 0: Direct
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the address supplied
• Cycle 1B: The host ASIC continues to apply the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the address
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data array, the mask array, or the register location
• Cycle 3: Idle cycle.
[67:30]
on the DQ bus. The host ASIC also supplies the GMR Index to mask the write to the data or mask array location on CMD[5:3].
For SRAM Writes, the host ASIC must supply SADR[21:19] on CMD[8:6].
supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask array
locations in CMD[5:3]. The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the devices
when DQ[25:21] = 11111.
of the selected device.
DQ
DQ[67:26]
Reserved
1: Indirect
1: Indirect
1: Indirect
[29]
DQ
CMD[1:0]
CMD[8:2]
CMDV
CLK2X
PHS_L
DQ
SSR (applicable if
DQ[29] is indirect)
SSR (applicable if
DQ[29] is indirect)
SSR (applicable if
DQ[29] is indirect)
[28:26]
DQ[25:21]
DQ
ID
cycle 0
[25:21]
Figure 12-3. Single Write Cycle Timing
DQ
ID
ID
ID
A
cycle 1
Address
External
Write
[20:19]
SRAM
11: Register
Array
Mask
Array
Data
DQ[20:19]
DQ
00:
01:
10:
B
Note
Reserved If DQ[29] is 0, this field carries the address of the data
Reserved If DQ[29] is 0, this field carries the address of the
Reserved If DQ[29] is 0, this field carries the address of the
[18:14]
. The latency of the SRAM Write will be different than the one
cycle 2
DQ
Data
array location. If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of the data
array location: {SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}.
mask array location. If DQ[29] is 1, the SSR specified
on DQ[28:26] is used to generate the address of the
mask array location: {SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}.
SRAM location. If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of the
SRAM location: {SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.
DQ[18:6]
Reserved
cycle 3
[6]
X
[6]
[6]
DQ[13:0]
cycle 4
Register address
CYNSE70032
DQ[5:0]
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