t6020m ATMEL Corporation, t6020m Datasheet - Page 46

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

Serial Receive Buffer (SRB) – Byte Read
The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads
content into the receive buffer when complete telegram has been received.
3.3.4
The UTCM consists of one timer (Timer 2) and a serial interface. There is a multitude of modes in which the timers
and serial interface can work together.
The 8-bit wide serial interface operates as shift register for modulation. The modulator units work together with the
timer and shift the data bits into or out of the shift register.
Combination Mode Timer 2 and SSI
T6020M
46 (54)
SRB
reserved
T2I
SYSCL
T1OUT
SCL
Combination Modes
First read cycle
Second read cycle
T2C
CL2/1
I/O–bus
RES
4-bit Counter 2/1
Compare 2/1
T1OUT
SYSCL
T2CO1
POUT
P4CR
TOG2
OVF1
Figure 49. Combination Timer 2 and SSI
Bit 7
Bit 3
SIC1
SCLI
SCL
POUT
TOG2
POUT
Timer 2 – control
Shift_CL
CM1
Bit 6
Bit 2
CL2/2
SO
T2M1
T2CM
SIC2
Transmit
buffer
MSB
DCG
STB
SSI–control
8-bit shift register
Bit 5
Bit 1
DCGO
RES
I/O–bus
8-bit Counter 2/2
Compare 2/2
T2CO2
SISC
SRB
Bit 4
Bit 0
Primary register address: ’9’hex
I/O–bus
OVF2
LSB
Receive
buffer
TOG2
INT4
Control
SI
INT3
SO
Output
MOUT
SO
Manchester–
modulator
OUTPUT
Biphase–,
T2M2
Reset value: xxxxb
Reset value: xxxxb
Rev. A3, 02-Apr-01
Control
output–stage
modulator
Timer 2
14222
T2O
SC
SD