t6020m ATMEL Corporation, t6020m Datasheet - Page 37

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for
the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2.
The timer compares the contents of the compare register
current counter value and if it matches it generates an
output signal. Dependent on the timer mode, this signal
is used to generate a timer interrupt, to toggle the output
flip-flop as SSI clock or as a clock for the next counter
Timer 2 Compare Mode Register (T2CM)
Timer 2 COmpare Register 1 (T2CO1)
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Timer 2 COmpare Register 2 (T2CO2) Byte Write
Rev. A3, 02-Apr-01
T2CM
T2OTM
T2CTM
T2RM
T2IM
T2CO1
T2CO2
Timer 2 Overflow Toggle Mask bit
T2OTM = 0, disable overflow toggle
T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2).
Timer 2 Compare Toggle Mask bit
T2CTM = 0, disable compare toggle
T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles out-
Timer 2 Reset Mask bit
T2RM = 0,
T2RM = 1, enable counter reset, a match of the counter with the compare register resets the counter
Timer 2 Interrupt Mask bit
T2IM = 0,
T2IM = 1,
Write cycle
First write cycle
Second write cycle
Timer 2 Output Mode
T2OTM
1, 2, 3, 4, 5 and 6
1, 2, 3, 4, 5 and 6
Bit 3
If the T2OTM-bit is set, only a counter overflow can generate an interrupt except on
the Timer 2 output mode 7.
put flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM-bit is set, only
a match of the counter with the compare register can generate an interrupt.
disable counter reset
disable Timer 2 interrupt
enable Timer 2 interrupt
7
T2CTM
Bit 2
Bit 3
Bit 3
Bit 7
T2RM
Bit 1
Bit 2
Bit 2
Bit 6
T2OTM
0
1
x
T2IM
stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and
T2CO2 bits 4 to 11 of the 12-bit compare value. In all
other
independently as a 4- and 8-bit compare register. When
assigned to the compare register a compare event will be
supressed.
Bit 0
Bit 1
Bit 1
Bit 5
modes, the two compare registers work
T2CTM
x
x
1
Bit 0
Bit 0
Bit 4
Address: ’7’hex – Subaddress: ’3’hex
Address: ’7’hex – Subaddress: ’4’hex
Address: ’7’hex – Subaddress: ’5’hex
Compare match (CM2)
Overflow (OVF2)
Compare match (CM2)
Timer 2 Interrupt Source
T6020M
Reset value: 0000b
Reset value: 1111b
Reset value: 1111b
Reset value: 1111b
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