t6020m ATMEL Corporation, t6020m Datasheet - Page 26

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

3.3.1
The Timer 1 is an interval timer which can be used to gen-
erate periodical interrupts and as prescaler for Timer 2,
Timer 3, the serial interface and the watchdog function.
The Timer 1 consists of a programmable 14-stage divider
that is driven by either SUBCL or SYSCL. The timer out-
put signal can be used as prescaler clock or as SUBCL and
as source for the Timer 1 interrupt. Because of other
system requirements the Timer 1 output T1OUT is
synchronized with SYSCL. Therefore in the power-down
mode SLEEP (CPU core –> sleep and OSC-Stop –> yes)
the output T1OUT is stopped (T1OUT=0). Nevertheless
the Timer 1 can be active in SLEEP and generate Timer 1
interrupts. The interrupt is maskable via the T1IM bit and
the SUBCL can be bypassed via the T1BP bit of the T1C2
register. The time interval for the timer output can be pro-
grammed via the Timer 1 control register T1C1.
This timer starts running automatically after any
T6020M
26 (54)
CL1
Write of the
T1C1 register
T1C1
Timer 1
WDC
T1RM T1C2 T1C1 T1C0
WDL WDR WDT1 WDT0
SUBCL
SYSCL
Decoder
Decoder
3
CL
RES
2
Q1 Q2 Q3 Q4
MUX
T1CS
CL1
mode control
Watchdog
Figure 25. Timer 1 and watchdog
RES
Figure 24. Timer 1 module
Q5
MUX for watchdog timer
MUX for interval timer
Prescaler
Q6
14 bit
T1MUX
Q8
Q8
power-on reset ! If the watchdog function is not activated,
the timer can be restarted by writing into the T1C1
register with T1RM=1.
Timer 1 can also be used as a watchdog timer to prevent
a system from stalling. The watchdog timer is a 3-bit
counter that is supplied by a separate output of Timer 1.
It generates a system reset when the 3-bit counter
overflows. To avoid this, the 3-bit counter must be reset
before it overflows. The application software has to
accomplish this by reading the CWD register.
After power-on reset the watchdog must be activated by
software in the $RESET initialization routine. There are
two watchdog modes, in one mode the watchdog can be
switched on and off by software, in the other mode the
watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval
for the watchdog reset can be programmed via the
watchdog control register (WDC).
WDCL
T1BP
Q11
Q11
T1IM
Watchdog
Q14
Q14
4 bit
T1C2
T1MUX
SUBCL
WDCL
T1BP T1IM
Divider / 8
Watchdog
NRST
INT2
T1OUT
Divider
RESET
13766
Rev. A3, 02-Apr-01
Read of the
CWD register
T1IM=0
T1IM=1
INT2
T1OUT
RESET
(NRST)
13767