sl28eb719 Silicon Laboratories, sl28eb719 Datasheet - Page 4

• Manufacturer Part Number: sl28eb719
• Description: Eproclock Generator For Intel Tunnel Creek & Top Cliff
• Manufacturer: Silicon Laboratories

DOC#: SP-AP-0005 (Rev. AB)
Frequency Select Pin (FS)
Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
Wake-On-LAN (WOL) Support
When power is applied to the VDD_SUSPEND pin, the 25MHz
reference clock output will be enabled under all conditions,
unless the WOL_EN bit, Byte 1 bit 1, is set to “0”. When the
WOL_EN bit Byte 1 bit 1, is set to “0”, the WOL_STP# pin will
function as a PD# pin. By default, the WOL_EN bit is enabled
and set to a “1”. The clock device will support “out-of-the-box”
WOL or after a power outage by enabling the 25MHz reference
clock output when the clock device powers up for the very first
time with only power applied to the VDD_SUSPEND pin and
all other VDD pins power have not been applied.
Table 1. Command Code Definition
SEL_SATA
(6:0)
Bit
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
FSC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
100.00
133.33
133.33
166.67
166.67
100.00
100.00
133.33
133.33
166.67
166.67
83.33
83.33
83.33
83.33
CPU
Description
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
SRC
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
SATA
75.00
75.00
75.00
75.00
75.00
75.00
75.00
75.00
SL28EB719
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
PCI
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